Merge pull request #3652 from chipsalliance/rvv_isastrs

Allow non-V implementations of vector units, with Zve/Zvl extensions

Author: jerryz123

Diff for: src/main/scala/rocket/CSR.scala

@@ -636,7 +636,7 @@ class CSRFile(
     (if (usingAtomics) "A" else "") +
     (if (fLen >= 32) "F" else "") +
     (if (fLen >= 64) "D" else "") +
-    (if (usingVector) "V" else "") +
+    (if (coreParams.hasV) "V" else "") +
     (if (usingCompressed) "C" else "")
   val isaString = (if (coreParams.useRVE) "E" else "I") +
     isaMaskString +

Diff for: src/main/scala/rocket/RocketCore.scala

@@ -66,6 +66,8 @@ case class RocketCoreParams(
   override val useVector = vector.isDefined
   override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false)
   override def vLen = vector.map(_.vLen).getOrElse(0)
+  override def eLen = vector.map(_.eLen).getOrElse(0)
+  override def vfLen = vector.map(_.vfLen).getOrElse(0)
   override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)
   override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
   override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)

Diff for: src/main/scala/rocket/VectorUnit.scala

@@ -10,6 +10,8 @@ import freechips.rocketchip.tilelink._
 case class RocketCoreVectorParams(
   build: Parameters => RocketVectorUnit,
   vLen: Int,
+  eLen: Int,
+  vfLen: Int,
   vMemDataBits: Int,
   decoder: Parameters => RocketVectorDecoder,
   useDCache: Boolean,

Diff for: src/main/scala/tile/BaseTile.scala

@@ -104,8 +104,17 @@ trait HasNonDiplomaticTileParameters {
     val f = if (tileParams.core.fpu.nonEmpty) "f" else ""
     val d = if (tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen > 32) "d" else ""
     val c = if (tileParams.core.useCompressed) "c" else ""
-    val v = if (tileParams.core.useVector) "v" else ""
+    val v = if (tileParams.core.useVector && tileParams.core.vLen >= 128 && tileParams.core.eLen == 64 && tileParams.core.vfLen == 64) "v" else ""
     val h = if (usingHypervisor) "h" else ""
+    val zvl = Option.when(tileParams.core.useVector) { Seq(s"zvl${tileParams.core.vLen}b") }
+    val zve = Option.when(tileParams.core.useVector) {
+      val c = tileParams.core.vfLen match {
+        case 64 => "d"
+        case 32 => "f"
+        case 0 => "x"
+      }
+      Seq(s"zve${tileParams.core.eLen}$c")
+    }
     val multiLetterExt = (
       // rdcycle[h], rdinstret[h] is implemented
       // rdtime[h] is not implemented, and could be provided by software emulation
@@ -114,6 +123,8 @@ trait HasNonDiplomaticTileParameters {
       Option.when(tileParams.core.useConditionalZero)(Seq("zicond")) ++
       Some(Seq("zicsr", "zifencei", "zihpm")) ++
       Option.when(tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen >= 16 && tileParams.core.fpu.get.minFLen <= 16)(Seq("zfh")) ++
+      zvl ++
+      zve ++
       tileParams.core.customIsaExt.map(Seq(_))
     ).flatten
     val multiLetterString = multiLetterExt.mkString("_")

Diff for: src/main/scala/tile/Core.scala

@@ -63,9 +63,11 @@ trait CoreParams {
   def dcacheReqTagBits: Int = 6
 
   def minFLen: Int = 32
+
   def vLen: Int = 0
-  def sLen: Int = 0
-  def eLen(xLen: Int, fLen: Int): Int = xLen max fLen
+  def eLen: Int = 0
+  def vfLen: Int = 0
+  def hasV: Boolean = vLen >= 128 && eLen >= 64 && vfLen >= 64
   def vMemDataBits: Int = 0
 }
 
@@ -106,14 +108,16 @@ trait HasCoreParameters extends HasTileParameters {
   val traceHasWdata = coreParams.traceHasWdata
 
   def vLen = coreParams.vLen
-  def sLen = coreParams.sLen
-  def eLen = coreParams.eLen(xLen, fLen)
+  def eLen = coreParams.eLen
+  def vfLen = coreParams.vfLen
   def vMemDataBits = if (usingVector) coreParams.vMemDataBits else 0
   def maxVLMax = vLen
 
   if (usingVector) {
     require(isPow2(vLen), s"vLen ($vLen) must be a power of 2")
     require(eLen >= 32 && vLen % eLen == 0, s"eLen must divide vLen ($vLen) and be no less than 32")
+    require(eLen == 32 || eLen == 64)
+    require(vfLen <= eLen)
   }
 
   lazy val hartIdLen: Int = p(MaxHartIdBits)