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jerryz123jerryz123
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Merge remote-tracking branch 'origin/dev' into merged_tl_credited
2 parents df74ae8 + c9289f5 commit d0b8b80

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Diff for: ‎.github/workflows/mill-ci.yml

+1-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ jobs:
2525
runs-on: ubuntu-latest
2626
strategy:
2727
matrix:
28-
config: [DefaultConfig, DefaultBufferlessConfig, DefaultRV32Config, TinyConfig, DefaultFP16Config]
28+
config: [DefaultConfig, DefaultBufferlessConfig, DefaultRV32Config, TinyConfig, DefaultFP16Config, DefaultBConfig, DefaultRV32BConfig]
2929
steps:
3030
- uses: actions/checkout@v2
3131
with:

Diff for: ‎RocketChip_Technical_Charter_8-23-2024.pdf

384 KB
Binary file not shown.

Diff for: ‎build.sc

+77-5
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ object v {
1212
val scala = "2.13.12"
1313
// the first version in this Map is the mainly supported version which will be used to run tests
1414
val chiselCrossVersions = Map(
15-
"5.1.0" -> (ivy"org.chipsalliance::chisel:5.1.0", ivy"org.chipsalliance:::chisel-plugin:5.1.0"),
15+
"6.7.0" -> (ivy"org.chipsalliance::chisel:6.7.0", ivy"org.chipsalliance:::chisel-plugin:6.7.0"),
1616
// build from project from source
1717
"source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"),
1818
)
@@ -185,6 +185,35 @@ trait Emulator extends Cross.Module2[String, String] {
185185
}
186186
}
187187

188+
object litexgenerate extends Module {
189+
def compile = T {
190+
os.proc("firtool",
191+
generator.chirrtl().path,
192+
s"--annotation-file=${generator.chiselAnno().path}",
193+
"--disable-annotation-unknown",
194+
"-dedup",
195+
"-O=debug",
196+
"--split-verilog",
197+
"--preserve-values=named",
198+
"--output-annotation-file=mfc.anno.json",
199+
"--lowering-options=disallowLocalVariables",
200+
s"-o=${T.dest}"
201+
).call(T.dest)
202+
PathRef(T.dest)
203+
}
204+
205+
def rtls = T {
206+
os.read(compile().path / "filelist.f").split("\n").map(str =>
207+
try {
208+
os.Path(str)
209+
} catch {
210+
case e: IllegalArgumentException if e.getMessage.contains("is not an absolute path") =>
211+
compile().path / str.stripPrefix("./")
212+
}
213+
).filter(p => p.ext == "v" || p.ext == "sv").map(PathRef(_)).toSeq
214+
}
215+
}
216+
188217
object mfccompiler extends Module {
189218
def compile = T {
190219
os.proc("firtool",
@@ -233,7 +262,7 @@ trait Emulator extends Cross.Module2[String, String] {
233262
"debug_rob.cc",
234263
"emulator.cc",
235264
"remote_bitbang.cc",
236-
).map(c => PathRef(csrcDir().path / c))
265+
).map(c => PathRef(csrcDir().path / c))
237266
}
238267

239268
def CMakeListsString = T {
@@ -316,6 +345,7 @@ object emulator extends Cross[Emulator](
316345
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBufferlessConfig"),
317346
// RocketSuiteC
318347
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig"),
348+
319349
// Unittest
320350
("freechips.rocketchip.unittest.TestHarness", "freechips.rocketchip.unittest.AMBAUnitTestConfig"),
321351
("freechips.rocketchip.unittest.TestHarness", "freechips.rocketchip.unittest.TLSimpleUnitTestConfig"),
@@ -343,6 +373,42 @@ object emulator extends Cross[Emulator](
343373
//
344374
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
345375
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
376+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig"),
377+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig"),
378+
379+
// Litex
380+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x1"),
381+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x2"),
382+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x4"),
383+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x8"),
384+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x1"),
385+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x2"),
386+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x4"),
387+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x8"),
388+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x1"),
389+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x2"),
390+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x4"),
391+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x8"),
392+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x1"),
393+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x2"),
394+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x4"),
395+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x8"),
396+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x1"),
397+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x2"),
398+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x4"),
399+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x8"),
400+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x1"),
401+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x2"),
402+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x4"),
403+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x8"),
404+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x1"),
405+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x2"),
406+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x4"),
407+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x8"),
408+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x1"),
409+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x2"),
410+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x4"),
411+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x8"),
346412
)
347413

348414
object `runnable-riscv-test` extends mill.Cross[RiscvTest](
@@ -404,8 +470,8 @@ object `runnable-riscv-test` extends mill.Cross[RiscvTest](
404470
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32uc-v", "none"),
405471
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32uf-p", "none"),
406472
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32uf-v", "none"),
407-
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32ui-p", "none"),
408-
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32ui-v", "none"),
473+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32ui-p", "ma_data"),
474+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32ui-v", "ma_data"),
409475
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32um-p", "none"),
410476
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "rv32um-v", "none"),
411477

@@ -417,11 +483,17 @@ object `runnable-riscv-test` extends mill.Cross[RiscvTest](
417483
// lsrc is not implemented if usingDataScratchpad
418484
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig", "rv32ua-p", "lrsc"),
419485
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig", "rv32uc-p", "none"),
420-
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig", "rv32ui-p", "none"),
486+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig", "rv32ui-p", "ma_data"),
421487
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig", "rv32um-p", "none"),
422488

423489
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config", "rv64uzfh-p", "none"),
424490
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config", "rv64uzfh-v", "none"),
491+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig", "rv64uzba-p", "none"),
492+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig", "rv64uzbb-p", "none"),
493+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig", "rv64uzbs-p", "none"),
494+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig", "rv32uzba-p", "none"),
495+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig", "rv32uzbb-p", "none"),
496+
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig", "rv32uzbs-p", "none"),
425497
)
426498

427499
object `runnable-arch-test` extends mill.Cross[ArchTest](

Diff for: ‎overlay.nix

+2-2
Original file line numberDiff line numberDiff line change
@@ -8,12 +8,12 @@ final: prev: {
88
});
99
riscvTests = final.pkgsCross.riscv64-embedded.stdenv.mkDerivation rec {
1010
pname = "riscv-tests";
11-
version = "55bbcc8c06637a31cc01970881ba8072838a9121";
11+
version = "f2f748ebb9cf8ea049103f85c4cbf7e8a2927b16";
1212
src = final.fetchgit {
1313
url = "https://github.com/riscv-software-src/riscv-tests.git";
1414
rev = "${version}";
1515
fetchSubmodules = true;
16-
sha256 = "sha256-TcIU+WFQxPqAG7lvfKPgHm4CnBpTkosqe+fYOxS+J7I=";
16+
sha256 = "sha256-E3RfrP+PFIYy9c/pY04jYPxeGpnfgWwjV8iwL5+s+9w=";
1717
};
1818

1919
enableParallelBuilding = true;

Diff for: ‎src/main/resources/vsrc/TraceSinkMonitor.v

+36
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
module TraceSinkMonitor
2+
#(
3+
parameter FILE_NAME = "trace_sink_monitor.txt"
4+
)
5+
(
6+
input clk,
7+
input reset,
8+
input in_fire,
9+
input[7:0] in_byte
10+
);
11+
12+
`ifndef SYNTHESIS
13+
14+
integer file;
15+
16+
initial begin
17+
file = $fopen(FILE_NAME, "w");
18+
if (file == 0) begin
19+
$display("Failed to open %s", FILE_NAME);
20+
$finish;
21+
end
22+
end
23+
24+
always @(posedge clk) begin
25+
if (in_fire & ~reset) begin
26+
$fwrite(file, "%c", in_byte);
27+
end
28+
end
29+
30+
final begin
31+
$fclose(file);
32+
end
33+
34+
`endif
35+
36+
endmodule

Diff for: ‎src/main/scala/amba/ahb/Xbar.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
2121
requestKeys = seq.flatMap(_.requestKeys).distinct,
2222
responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
2323
){
24-
override def circuitIdentity = outputs == 1 && inputs == 1
24+
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
2525
}
2626

2727
lazy val module = new Impl

Diff for: ‎src/main/scala/amba/apb/Xbar.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
2121
requestKeys = seq.flatMap(_.requestKeys).distinct,
2222
responseFields = BundleField.union(seq.flatMap(_.responseFields))) }
2323
){
24-
override def circuitIdentity = outputs == 1 && inputs == 1
24+
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
2525
}
2626

2727
lazy val module = new Impl

Diff for: ‎src/main/scala/amba/axi4/Buffer.scala

+12
Original file line numberDiff line numberDiff line change
@@ -68,4 +68,16 @@ object AXI4Buffer
6868
val axi4buf = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
6969
axi4buf.node
7070
}
71+
72+
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[AXI4Node] = {
73+
val buffers = Seq.fill(depth) { LazyModule(new AXI4Buffer()) }
74+
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
75+
buffers.map(_.node)
76+
}
77+
78+
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): AXI4Node = {
79+
chain(depth, name)
80+
.reduceLeftOption(_ :*=* _)
81+
.getOrElse(AXI4NameNode("no_buffer"))
82+
}
7183
}

Diff for: ‎src/main/scala/amba/axi4/Xbar.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ class AXI4Xbar(
5353
)
5454
}
5555
){
56-
override def circuitIdentity = outputs == 1 && inputs == 1
56+
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
5757
}
5858

5959
lazy val module = new Impl

Diff for: ‎src/main/scala/devices/debug/Debug.scala

+3-4
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDes
1919
import freechips.rocketchip.rocket.{CSRs, Instructions}
2020
import freechips.rocketchip.tile.MaxHartIdBits
2121
import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
22-
import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
22+
import freechips.rocketchip.util.{AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
2323

2424
import freechips.rocketchip.util.SeqBoolBitwiseOps
2525
import freechips.rocketchip.util.SeqToAugmentedSeq
@@ -660,7 +660,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
660660
val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt))
661661

662662
for (component <- 0 until nComponents) {
663-
hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component)
663+
hartResetNxt(component) := DMCONTROLNxt.hartreset & hartSelected(component)
664664
io.hartResetReq.get(component) := hartResetReg(component)
665665
}
666666
}
@@ -672,7 +672,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
672672

673673
val cfg = p(DebugModuleKey).get
674674

675-
val dmiXbar = LazyModule (new TLXbar())
675+
val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar")))
676676

677677
val dmi2tlOpt = (!p(ExportDebug).apb).option({
678678
val dmi2tl = LazyModule(new DMIToTL())
@@ -789,7 +789,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
789789
lazy val module = new Impl
790790
class Impl extends LazyModuleImp(this){
791791
val nComponents = getNComponents()
792-
Annotated.params(this, cfg)
793792
val supportHartArray = cfg.supportHartArray & (nComponents > 1)
794793
val nExtTriggers = cfg.nExtTriggers
795794
val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups

Diff for: ‎src/main/scala/devices/debug/Periphery.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ trait HasPeripheryDebug { this: BaseSubsystem =>
8787
lazy val debugOpt = p(DebugModuleKey).map { params =>
8888
val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
8989

90-
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus) := _ }
90+
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ }
9191
tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
9292

9393
(apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) =>

Diff for: ‎src/main/scala/devices/tilelink/BootROM.scala

+32-14
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
1313
import freechips.rocketchip.resources.{Resource, SimpleDevice}
1414
import freechips.rocketchip.subsystem._
1515
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
16+
import freechips.rocketchip.util.{FileName, SystemFileName, ResourceFileName}
1617

1718
import java.nio.ByteBuffer
1819
import java.nio.file.{Files, Paths}
@@ -22,7 +23,11 @@ case class BootROMParams(
2223
address: BigInt = 0x10000,
2324
size: Int = 0x10000,
2425
hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector
25-
contentFileName: String)
26+
driveResetVector: Boolean = true,
27+
appendDTB: Boolean = true,
28+
name: String = "bootrom",
29+
contentFileName: FileName = SystemFileName("./bootrom/bootrom.img")
30+
)
2631

2732
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
2833
resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
@@ -63,7 +68,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
6368
}
6469
}
6570

66-
case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)
71+
case class BootROMLocated(loc: HierarchicalLocation) extends Field[Seq[BootROMParams]](Nil)
6772

6873
object BootROM {
6974
/** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect
@@ -73,27 +78,40 @@ object BootROM {
7378
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
7479
(implicit p: Parameters): TLROM = {
7580
val tlbus = subsystem.locateTLBusWrapper(where)
76-
val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
81+
val bootROMDomainWrapper = tlbus.generateSynchronousDomain(params.name).suggestName(s"${params.name}_domain")
7782

7883
val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
79-
lazy val contents = {
80-
val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
81-
val rom = ByteBuffer.wrap(romdata)
82-
rom.array() ++ subsystem.dtb.contents
84+
val rom = params.contentFileName match {
85+
case SystemFileName(fileName) => {
86+
val romdata = Files.readAllBytes(Paths.get(fileName))
87+
ByteBuffer.wrap(romdata).array()
88+
}
89+
case ResourceFileName(fileName) => {
90+
val file = os.resource / os.RelPath(fileName.dropWhile(_ == '/'))
91+
os.read.bytes(file)
92+
}
93+
}
94+
95+
lazy val contents = if (params.appendDTB) {
96+
rom ++ subsystem.dtb.contents
97+
} else {
98+
rom
8399
}
84100

85101
val bootrom = bootROMDomainWrapper {
86102
LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
87103
}
88104

89-
bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus) := _ }
105+
bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }
90106
// Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
91-
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
92-
InModuleBody {
93-
val reset_vector_source = bootROMResetVectorSourceNode.bundle
94-
require(reset_vector_source.getWidth >= params.hang.bitLength,
95-
s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
96-
bootROMResetVectorSourceNode.bundle := params.hang.U
107+
if (params.driveResetVector) {
108+
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
109+
InModuleBody {
110+
val reset_vector_source = bootROMResetVectorSourceNode.bundle
111+
require(reset_vector_source.getWidth >= params.hang.bitLength,
112+
s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
113+
bootROMResetVectorSourceNode.bundle := params.hang.U
114+
}
97115
}
98116
bootrom
99117
}

Diff for: ‎src/main/scala/devices/tilelink/CLINT.scala

+1-3
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSink
1414
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
1515
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
1616
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
17-
import freechips.rocketchip.util.Annotated
1817

1918
object CLINTConsts
2019
{
@@ -63,7 +62,6 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
6362

6463
lazy val module = new Impl
6564
class Impl extends LazyModuleImp(this) {
66-
Annotated.params(this, params)
6765
require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
6866

6967
val io = IO(new Bundle {
@@ -110,7 +108,7 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem =>
110108
val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
111109
val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain")
112110
val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
113-
clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ } }
111+
clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } }
114112
val clintTick = clintDomainWrapper { InModuleBody {
115113
val tick = IO(Input(Bool()))
116114
clint.module.io.rtcTick := tick

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