Merge pull request #3707 from chipsalliance/vsew_fix

VectorDecoder in FPU may need to check v_sew'
chipsalliance · Jan 29, 2025 · dac1f10 · dac1f10
2 parents 8fa6290 + 5e1d66f
commit dac1f10
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Showing 3 changed files with 4 additions and 1 deletion.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -351,6 +351,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     val v_decode = rocketParams.vector.get.decoder(p)
     v_decode.io.inst := id_inst(0)
     v_decode.io.vconfig := csr.io.vector.get.vconfig
+    id_ctrl.vec := v_decode.io.vector
     when (v_decode.io.legal) {
       id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
       id_ctrl.fp := v_decode.io.fp

diff --git a/src/main/scala/rocket/VectorUnit.scala b/src/main/scala/rocket/VectorUnit.scala
@@ -91,7 +91,8 @@ abstract class RocketVectorDecoder(implicit p: Parameters) extends CoreModule()(
   val io = IO(new Bundle {
     val inst = Input(UInt(32.W))
     val vconfig = Input(new VConfig)
-    val legal = Output(Bool())
+    val vector = Output(Bool()) // this is a vector instruction
+    val legal = Output(Bool()) // this is a legal vector instruction given vconfig
     val fp = Output(Bool())
     val read_rs1 = Output(Bool())
     val read_rs2 = Output(Bool())

diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
@@ -754,6 +754,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
     val v_decode = v.decoder(p) // Only need to get ren1
     v_decode.io.inst := io.inst
     v_decode.io.vconfig := DontCare // core deals with this
+    v_decode.io.vconfig.vtype.vsew := io.v_sew
     when (v_decode.io.legal && v_decode.io.read_frs1) {
       id_ctrl.ren1 := true.B
       id_ctrl.swap12 := false.B