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jerryz123jerryz123
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Merge pull request #3641 from chipsalliance/naming
Set parameterized desiredName on many system componets
2 parents 043926a + ee00619 commit ea9979b

33 files changed

+89
-36
lines changed

Diff for: ‎src/main/scala/devices/debug/Debug.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -672,7 +672,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
672672

673673
val cfg = p(DebugModuleKey).get
674674

675-
val dmiXbar = LazyModule (new TLXbar())
675+
val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar")))
676676

677677
val dmi2tlOpt = (!p(ExportDebug).apb).option({
678678
val dmi2tl = LazyModule(new DMIToTL())

Diff for: ‎src/main/scala/devices/debug/Periphery.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ trait HasPeripheryDebug { this: BaseSubsystem =>
8787
lazy val debugOpt = p(DebugModuleKey).map { params =>
8888
val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
8989

90-
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus) := _ }
90+
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ }
9191
tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
9292

9393
(apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) =>

Diff for: ‎src/main/scala/devices/tilelink/BootROM.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ object BootROM {
8686
LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
8787
}
8888

89-
bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus) := _ }
89+
bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }
9090
// Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
9191
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
9292
InModuleBody {

Diff for: ‎src/main/scala/devices/tilelink/CLINT.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem =>
110110
val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
111111
val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain")
112112
val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
113-
clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ } }
113+
clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } }
114114
val clintTick = clintDomainWrapper { InModuleBody {
115115
val tick = IO(Input(Bool()))
116116
clint.module.io.rtcTick := tick

Diff for: ‎src/main/scala/devices/tilelink/Plic.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -365,7 +365,7 @@ trait CanHavePeripheryPLIC { this: BaseSubsystem =>
365365
val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
366366

367367
val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
368-
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus) := _ } }
368+
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } }
369369
plicDomainWrapper { plic.intnode :=* ibus.toPLIC }
370370

371371
(plic, plicDomainWrapper)

Diff for: ‎src/main/scala/interrupts/Crossing.scala

+9
Original file line numberDiff line numberDiff line change
@@ -39,11 +39,15 @@ class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Para
3939
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
4040

4141
class Impl extends LazyModuleImp(this) {
42+
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
43+
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
4244
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
4345
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
4446
}
4547
}
4648
class ImplRegistered extends LazyRawModuleImp(this) {
49+
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
50+
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
4751
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
4852
out.sync := in
4953
}
@@ -68,6 +72,7 @@ class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends La
6872

6973
lazy val module = new Impl
7074
class Impl extends LazyModuleImp(this) {
75+
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
7176
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
7277
out := SynchronizerShiftReg(in.sync, sync)
7378
}
@@ -89,6 +94,8 @@ class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
8994

9095
lazy val module = new Impl
9196
class Impl extends LazyRawModuleImp(this) {
97+
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
98+
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
9299
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
93100
out := in.sync
94101
}
@@ -110,6 +117,8 @@ class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
110117

111118
lazy val module = new Impl
112119
class Impl extends LazyModuleImp(this) {
120+
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
121+
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
113122
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
114123
out := RegNext(in.sync)
115124
}

Diff for: ‎src/main/scala/interrupts/Xbar.scala

+2
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ class IntXbar()(implicit p: Parameters) extends LazyModule
2020

2121
lazy val module = new Impl
2222
class Impl extends LazyRawModuleImp(this) {
23+
override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}"
2324
val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
2425
intnode.out.foreach { case (o, _) => o := cat }
2526
}
@@ -40,6 +41,7 @@ class IntSyncXbar()(implicit p: Parameters) extends LazyModule
4041

4142
lazy val module = new Impl
4243
class Impl extends LazyModuleImp(this) {
44+
override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}"
4345
val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten
4446
intnode.out.foreach { case (o, _) => o.sync := cat }
4547
}

Diff for: ‎src/main/scala/jtag/JtagShifter.scala

+2
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,7 @@ object JtagBypassChain {
8787
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
8888
*/
8989
class CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {
90+
override def desiredName = s"CaptureChain_${gen.typeName}"
9091
class ModIO extends ChainIO {
9192
val capture = Capture(gen)
9293
}
@@ -134,6 +135,7 @@ object CaptureChain {
134135
* 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge
135136
*/
136137
class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {
138+
override def desiredName = s"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}"
137139
class ModIO extends ChainIO {
138140
val capture = Capture(genCapture)
139141
val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after

Diff for: ‎src/main/scala/prci/ClockGroup.scala

+2-1
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
4848
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
4949
{
5050
val node = ClockGroupAggregateNode(groupName)
51-
51+
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
5252
lazy val module = new Impl
5353
class Impl extends LazyRawModuleImp(this) {
5454
val (in, _) = node.in.unzip
@@ -104,6 +104,7 @@ class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Pa
104104
class Impl extends LazyRawModuleImp(this) {
105105
val (in, _) = node.in(0)
106106
val (out, _) = node.out.unzip
107+
override def desiredName = s"FixedClockBroadcast_${out.size}"
107108
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
108109
out.foreach { _ := in }
109110
}

Diff for: ‎src/main/scala/prci/ResetStretcher.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ import org.chipsalliance.diplomacy.lazymodule._
1414
class ResetStretcher(cycles: Int)(implicit p: Parameters) extends LazyModule {
1515
val node = ClockAdapterNode()(ValName("reset_stretcher"))
1616
require(cycles > 1, s"ResetStretcher only supports cycles > 1 but got ${cycles}")
17-
17+
override lazy val desiredName = s"ResetStretcher$cycles"
1818
lazy val module = new Impl
1919
class Impl extends LazyModuleImp(this) {
2020
(node.in zip node.out).foreach { case ((in, _), (out, _)) =>

Diff for: ‎src/main/scala/regmapper/RegMapper.scala

+7-1
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,13 @@ object RegMapper
6767
val depth = concurrency
6868
require (depth >= 0)
6969
require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0")
70-
val back = if (depth > 0) Queue(front, depth) else front
70+
val back = if (depth > 0) {
71+
val front_q = Module(new Queue(new RegMapperInput(inParams), depth) {
72+
override def desiredName = s"Queue${depth}_${front.bits.typeName}_i${inParams.indexBits}_m${inParams.maskBits}"
73+
})
74+
front_q.io.enq <> front
75+
front_q.io.deq
76+
} else front
7177

7278
// Convert to and from Bits
7379
def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =

Diff for: ‎src/main/scala/rocket/DCache.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
6060
val data_arrays = Seq.tabulate(rowBits / subWordBits) {
6161
i =>
6262
DescribedSRAM(
63-
name = s"data_arrays_${i}",
63+
name = s"${tileParams.baseName}_dcache_data_arrays_${i}",
6464
desc = "DCache Data Array",
6565
size = nSets * cacheBlockBytes / rowBytes,
6666
data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W))
@@ -135,7 +135,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
135135
val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance)
136136

137137
val tag_array = DescribedSRAM(
138-
name = "tag_array",
138+
name = s"${tileParams.baseName}_dcache_tag_array",
139139
desc = "DCache Tag Array",
140140
size = nSets,
141141
data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data))

Diff for: ‎src/main/scala/rocket/ICache.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -418,7 +418,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
418418
* content with `refillError ## tag[19:0]` after ECC
419419
* */
420420
val tag_array = DescribedSRAM(
421-
name = "tag_array",
421+
name = s"${tileParams.baseName}_icache_tag_array",
422422
desc = "ICache Tag Array",
423423
size = nSets,
424424
data = Vec(nWays, UInt(tECC.width(1 + tagBits).W))
@@ -552,7 +552,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
552552
val data_arrays = Seq.tabulate(tl_out.d.bits.data.getWidth / wordBits) {
553553
i =>
554554
DescribedSRAM(
555-
name = s"data_arrays_${i}",
555+
name = s"${tileParams.baseName}_icache_data_arrays_${i}",
556556
desc = "ICache Data Array",
557557
size = nSets * refillCycles,
558558
data = Vec(nWays, UInt(dECC.width(wordBits).W))

Diff for: ‎src/main/scala/rocket/PMP.scala

+1
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
142142

143143
class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module
144144
with HasCoreParameters {
145+
override def desiredName = s"PMPChecker_s${lgMaxSize}"
145146
val io = IO(new Bundle {
146147
val prv = Input(UInt(PRV.SZ.W))
147148
val pmp = Input(Vec(nPMPs, new PMP))

Diff for: ‎src/main/scala/rocket/RocketCore.scala

+4-2
Original file line numberDiff line numberDiff line change
@@ -751,10 +751,12 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
751751
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
752752
val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
753753

754-
val ll_arb = Module(new Arbiter(new Bundle {
754+
class LLWB extends Bundle {
755755
val data = UInt(xLen.W)
756756
val tag = UInt(5.W)
757-
}, 3)) // div, rocc, vec
757+
}
758+
759+
val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec
758760
ll_arb.io.in.foreach(_.valid := false.B)
759761
ll_arb.io.in.foreach(_.bits := DontCare)
760762
val ll_wdata = WireInit(ll_arb.io.out.bits.data)

Diff for: ‎src/main/scala/rocket/TLB.scala

+1
Original file line numberDiff line numberDiff line change
@@ -317,6 +317,7 @@ case class TLBConfig(
317317
* @param edge collect SoC metadata.
318318
*/
319319
class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
320+
override def desiredName = if (instruction) "ITLB" else "DTLB"
320321
val io = IO(new Bundle {
321322
/** request from Core */
322323
val req = Flipped(Decoupled(new TLBReq(lgMaxSize)))

Diff for: ‎src/main/scala/subsystem/HierarchicalElement.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,8 @@ abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implici
5252
def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement]
5353

5454
protected val tlOtherMastersNode = TLIdentityNode()
55-
protected val tlMasterXbar = LazyModule(new TLXbar)
56-
protected val tlSlaveXbar = LazyModule(new TLXbar)
55+
protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName")))
56+
protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName")))
5757
protected val intXbar = LazyModule(new IntXbar)
5858

5959
def masterNode: TLOutwardNode

Diff for: ‎src/main/scala/subsystem/MemoryBus.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p
4444
addressPrefixNexusNode
4545
}
4646

47-
private val xbar = LazyModule(new TLXbar).suggestName(busName + "_xbar")
47+
private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar")
4848
val inwardNode: TLInwardNode =
4949
replicator.map(xbar.node :*=* TLFIFOFixer(TLFIFOFixer.all) :*=* _.node)
5050
.getOrElse(xbar.node :*=* TLFIFOFixer(TLFIFOFixer.all))

Diff for: ‎src/main/scala/subsystem/PeripheryBus.scala

+5-4
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@ case class PeripheryBusParams(
4444
class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters)
4545
extends TLBusWrapper(params, name)
4646
{
47+
override lazy val desiredName = s"PeripheryBus_$name"
4748
private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r)))
4849
val prefixNode = replicator.map { r =>
4950
r.prefix := addressPrefixNexusNode
@@ -52,15 +53,15 @@ class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Paramet
5253

5354
private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
5455
private val node: TLNode = params.atomics.map { pa =>
55-
val in_xbar = LazyModule(new TLXbar)
56-
val out_xbar = LazyModule(new TLXbar)
56+
val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in")))
57+
val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out")))
5758
val fixer_node = replicator.map(fixer.node :*= _.node).getOrElse(fixer.node)
5859
(out_xbar.node
5960
:*= fixer_node
6061
:*= TLBuffer(pa.buffer)
6162
:*= (pa.widenBytes.filter(_ > beatBytes).map { w =>
62-
TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic)
63-
} .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic) })
63+
TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name))
64+
} .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) })
6465
:*= in_xbar.node)
6566
} .getOrElse { TLXbar() :*= fixer.node }
6667

Diff for: ‎src/main/scala/subsystem/SystemBus.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p
4444
addressPrefixNexusNode
4545
}
4646

47-
private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy))
47+
private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name)))
4848
val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode())
4949
val outwardNode: TLOutwardNode = system_bus_xbar.node
5050
def busView: TLEdge = system_bus_xbar.node.edges.in.head

Diff for: ‎src/main/scala/tile/FPU.scala

+2
Original file line numberDiff line numberDiff line change
@@ -632,6 +632,7 @@ class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) wi
632632

633633
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
634634
{
635+
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
635636
require(latency<=2)
636637

637638
val io = IO(new Bundle {
@@ -695,6 +696,7 @@ class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
695696

696697
class FPUFMAPipe(val latency: Int, val t: FType)
697698
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
699+
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
698700
require(latency>0)
699701

700702
val io = IO(new Bundle {

Diff for: ‎src/main/scala/tilelink/AsyncCrossing.scala

+2
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends L
2121

2222
lazy val module = new Impl
2323
class Impl extends LazyModuleImp(this) {
24+
override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_")
2425
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
2526
val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
2627
val psync = sync.getOrElse(edgeOut.manager.async.sync)
@@ -56,6 +57,7 @@ class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implici
5657

5758
lazy val module = new Impl
5859
class Impl extends LazyModuleImp(this) {
60+
override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
5961
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
6062
val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
6163

Diff for: ‎src/main/scala/tilelink/AtomicAutomata.scala

+4-2
Original file line numberDiff line numberDiff line change
@@ -284,9 +284,11 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
284284

285285
object TLAtomicAutomata
286286
{
287-
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
287+
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
288288
{
289-
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
289+
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) {
290+
override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_")
291+
})
290292
atomics.node
291293
}
292294

Diff for: ‎src/main/scala/tilelink/Buffer.scala

+2
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,8 @@ class TLBuffer(
3838

3939
lazy val module = new Impl
4040
class Impl extends LazyModuleImp(this) {
41+
def headBundle = node.out.head._2.bundle
42+
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
4143
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out.a <> a(in .a)
4345
in .d <> d(out.d)

Diff for: ‎src/main/scala/tilelink/Bundles.scala

+5
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,7 @@ sealed trait TLAddrChannel extends TLDataChannel
173173
final class TLBundleA(params: TLBundleParameters)
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extends TLBundleBase(params) with TLAddrChannel
175175
{
176+
override def typeName = s"TLBundleA_${params.shortName}"
176177
val channelName = "'A' channel"
177178
// fixed fields during multibeat:
178179
val opcode = UInt(3.W)
@@ -190,6 +191,7 @@ final class TLBundleA(params: TLBundleParameters)
190191
final class TLBundleB(params: TLBundleParameters)
191192
extends TLBundleBase(params) with TLAddrChannel
192193
{
194+
override def typeName = s"TLBundleB_${params.shortName}"
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val channelName = "'B' channel"
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// fixed fields during multibeat:
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val opcode = UInt(3.W)
@@ -206,6 +208,7 @@ final class TLBundleB(params: TLBundleParameters)
206208
final class TLBundleC(params: TLBundleParameters)
207209
extends TLBundleBase(params) with TLAddrChannel
208210
{
211+
override def typeName = s"TLBundleC_${params.shortName}"
209212
val channelName = "'C' channel"
210213
// fixed fields during multibeat:
211214
val opcode = UInt(3.W)
@@ -223,6 +226,7 @@ final class TLBundleC(params: TLBundleParameters)
223226
final class TLBundleD(params: TLBundleParameters)
224227
extends TLBundleBase(params) with TLDataChannel
225228
{
229+
override def typeName = s"TLBundleD_${params.shortName}"
226230
val channelName = "'D' channel"
227231
// fixed fields during multibeat:
228232
val opcode = UInt(3.W)
@@ -241,6 +245,7 @@ final class TLBundleD(params: TLBundleParameters)
241245
final class TLBundleE(params: TLBundleParameters)
242246
extends TLBundleBase(params) with TLChannel
243247
{
248+
override def typeName = s"TLBundleE_${params.shortName}"
244249
val channelName = "'E' channel"
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val sink = UInt(params.sinkBits.W) // to
246251
}

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