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Merge pull request #3639 from chipsalliance/named_domains
Name the ClockDomains
2 parents d9a3d99 + 3cec0f0 commit f43041d

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5 files changed

+8
-5
lines changed

5 files changed

+8
-5
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Diff for: src/main/scala/devices/tilelink/BootROM.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ object BootROM {
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def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
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(implicit p: Parameters): TLROM = {
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val tlbus = subsystem.locateTLBusWrapper(where)
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val bootROMDomainWrapper = tlbus.generateSynchronousDomain.suggestName("bootrom_domain")
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val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
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val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
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lazy val contents = {

Diff for: src/main/scala/devices/tilelink/CLINT.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
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trait CanHavePeripheryCLINT { this: BaseSubsystem =>
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val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params =>
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val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
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val clintDomainWrapper = tlbus.generateSynchronousDomain.suggestName("clint_domain")
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val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain")
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val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
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clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ } }
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val clintTick = clintDomainWrapper { InModuleBody {

Diff for: src/main/scala/devices/tilelink/Plic.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,7 @@ class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
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trait CanHavePeripheryPLIC { this: BaseSubsystem =>
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val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>
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val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
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val plicDomainWrapper = tlbus.generateSynchronousDomain.suggestName("plic_domain")
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val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
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val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
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plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus) := _ } }

Diff for: src/main/scala/prci/ClockDomain.scala

+2
Original file line numberDiff line numberDiff line change
@@ -34,13 +34,15 @@ class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Para
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def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
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val clockNode = ClockSinkNode(Seq(clockSinkParams))
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def clockBundle = clockNode.in.head._1
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override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
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}
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class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
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{
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def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
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val clockNode = ClockSourceNode(Seq(clockSourceParams))
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def clockBundle = clockNode.out.head._1
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override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
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}
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abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing

Diff for: src/main/scala/tilelink/BusWrapper.scala

+3-2
Original file line numberDiff line numberDiff line change
@@ -85,11 +85,12 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
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def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers)
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def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing"))
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def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing"))
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def generateSynchronousDomain: ClockSinkDomain = {
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val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt))
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def generateSynchronousDomain(domainName: String): ClockSinkDomain = {
89+
val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName)))
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domain.clockNode := fixedClockNode
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domain
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}
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def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("")
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protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W)))
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