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jerryz123jerryz123
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Merge pull request #3655 from chipsalliance/split-configs
Move rocket-related config fragments to rocket/Configs.scala
2 parents 1ba5acd + 0464c21 commit f50b0db

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12 files changed

+361
-600
lines changed

12 files changed

+361
-600
lines changed

Diff for: ‎src/main/scala/groundtest/Configs.scala

+3-3
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey}
1010
import freechips.rocketchip.subsystem._
1111
import freechips.rocketchip.system.BaseConfig
1212
import freechips.rocketchip.rocket.{DCacheParams}
13-
import freechips.rocketchip.tile.{XLen}
1413

1514
/** Actual testing target Configs */
1615

@@ -39,7 +38,8 @@ class WithTraceGen(
3938
n: Int = 2,
4039
overrideMemOffset: Option[BigInt] = None)(
4140
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
42-
nReqs: Int = 8192
41+
nReqs: Int = 8192,
42+
wordBits: Int = 32
4343
) extends Config((site, here, up) => {
4444
case TilesLocated(InSubsystem) => {
4545
val prev = up(TilesLocated(InSubsystem), site)
@@ -50,7 +50,7 @@ class WithTraceGen(
5050
tileParams = TraceGenParams(
5151
tileId = i + idOffset,
5252
dcache = Some(dcp),
53-
wordBits = site(XLen),
53+
wordBits = wordBits,
5454
addrBits = 32,
5555
addrBag = {
5656
val nSets = dcp.nSets

Diff for: ‎src/main/scala/groundtest/TraceGen.scala

+4-4
Original file line numberDiff line numberDiff line change
@@ -62,11 +62,11 @@ import freechips.rocketchip.prci.{ClockSinkParameters, ClockCrossingType}
6262
// to repeatedly recompile with a different address bag.)
6363

6464
case class TraceGenParams(
65-
wordBits: Int, // p(XLen)
66-
addrBits: Int, // p(PAddrBits)
67-
addrBag: List[BigInt], // p(AddressBag)
65+
wordBits: Int,
66+
addrBits: Int,
67+
addrBag: List[BigInt],
6868
maxRequests: Int,
69-
memStart: BigInt, //p(ExtMem).base
69+
memStart: BigInt,
7070
numGens: Int,
7171
dcache: Option[DCacheParams] = Some(DCacheParams()),
7272
tileId: Int = 0

Diff for: ‎src/main/scala/rocket/Configs.scala

+283
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,283 @@
1+
package freechips.rocketchip.rocket
2+
3+
import chisel3.util._
4+
5+
import org.chipsalliance.cde.config._
6+
import org.chipsalliance.diplomacy.lazymodule._
7+
8+
import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
9+
import freechips.rocketchip.subsystem.{TilesLocated, NumTiles, HierarchicalLocation, RocketCrossingParams, SystemBusKey, CacheBlockBytes, RocketTileAttachParams, InSubsystem, InCluster, HierarchicalElementMasterPortParams, HierarchicalElementSlavePortParams, CBUS, CCBUS, ClustersLocated, TileAttachConfig, CloneTileAttachParams}
10+
import freechips.rocketchip.tile.{RocketTileParams, RocketTileBoundaryBufferParams}
11+
import scala.reflect.ClassTag
12+
13+
14+
class WithNBigCores(
15+
n: Int,
16+
location: HierarchicalLocation,
17+
crossing: RocketCrossingParams,
18+
) extends Config((site, here, up) => {
19+
case TilesLocated(`location`) => {
20+
val prev = up(TilesLocated(`location`), site)
21+
val idOffset = up(NumTiles)
22+
val big = RocketTileParams(
23+
core = RocketCoreParams(mulDiv = Some(MulDivParams(
24+
mulUnroll = 8,
25+
mulEarlyOut = true,
26+
divEarlyOut = true))),
27+
dcache = Some(DCacheParams(
28+
rowBits = site(SystemBusKey).beatBits,
29+
nMSHRs = 0,
30+
blockBytes = site(CacheBlockBytes))),
31+
icache = Some(ICacheParams(
32+
rowBits = site(SystemBusKey).beatBits,
33+
blockBytes = site(CacheBlockBytes))))
34+
List.tabulate(n)(i => RocketTileAttachParams(
35+
big.copy(tileId = i + idOffset),
36+
crossing
37+
)) ++ prev
38+
}
39+
case NumTiles => up(NumTiles) + n
40+
}) {
41+
def this(n: Int, location: HierarchicalLocation = InSubsystem) = this(n, location, RocketCrossingParams(
42+
master = HierarchicalElementMasterPortParams.locationDefault(location),
43+
slave = HierarchicalElementSlavePortParams.locationDefault(location),
44+
mmioBaseAddressPrefixWhere = location match {
45+
case InSubsystem => CBUS
46+
case InCluster(clusterId) => CCBUS(clusterId)
47+
}
48+
))
49+
}
50+
51+
class WithNMedCores(
52+
n: Int,
53+
crossing: RocketCrossingParams = RocketCrossingParams(),
54+
) extends Config((site, here, up) => {
55+
case TilesLocated(InSubsystem) => {
56+
val prev = up(TilesLocated(InSubsystem), site)
57+
val idOffset = up(NumTiles)
58+
val med = RocketTileParams(
59+
core = RocketCoreParams(fpu = None),
60+
btb = None,
61+
dcache = Some(DCacheParams(
62+
rowBits = site(SystemBusKey).beatBits,
63+
nSets = 64,
64+
nWays = 1,
65+
nTLBSets = 1,
66+
nTLBWays = 4,
67+
nMSHRs = 0,
68+
blockBytes = site(CacheBlockBytes))),
69+
icache = Some(ICacheParams(
70+
rowBits = site(SystemBusKey).beatBits,
71+
nSets = 64,
72+
nWays = 1,
73+
nTLBSets = 1,
74+
nTLBWays = 4,
75+
blockBytes = site(CacheBlockBytes))))
76+
List.tabulate(n)(i => RocketTileAttachParams(
77+
med.copy(tileId = i + idOffset),
78+
crossing
79+
)) ++ prev
80+
}
81+
case NumTiles => up(NumTiles) + n
82+
})
83+
84+
class WithNSmallCores(
85+
n: Int,
86+
crossing: RocketCrossingParams = RocketCrossingParams()
87+
) extends Config((site, here, up) => {
88+
case TilesLocated(InSubsystem) => {
89+
val prev = up(TilesLocated(InSubsystem), site)
90+
val idOffset = up(NumTiles)
91+
val small = RocketTileParams(
92+
core = RocketCoreParams(useVM = false, fpu = None),
93+
btb = None,
94+
dcache = Some(DCacheParams(
95+
rowBits = site(SystemBusKey).beatBits,
96+
nSets = 64,
97+
nWays = 1,
98+
nTLBSets = 1,
99+
nTLBWays = 4,
100+
nMSHRs = 0,
101+
blockBytes = site(CacheBlockBytes))),
102+
icache = Some(ICacheParams(
103+
rowBits = site(SystemBusKey).beatBits,
104+
nSets = 64,
105+
nWays = 1,
106+
nTLBSets = 1,
107+
nTLBWays = 4,
108+
blockBytes = site(CacheBlockBytes))))
109+
List.tabulate(n)(i => RocketTileAttachParams(
110+
small.copy(tileId = i + idOffset),
111+
crossing
112+
)) ++ prev
113+
}
114+
case NumTiles => up(NumTiles) + n
115+
})
116+
117+
class With1TinyCore extends Config((site, here, up) => {
118+
case TilesLocated(InSubsystem) => {
119+
val tiny = RocketTileParams(
120+
core = RocketCoreParams(
121+
xLen = 32,
122+
pgLevels = 2, // sv32
123+
useVM = false,
124+
fpu = None,
125+
mulDiv = Some(MulDivParams(mulUnroll = 8))),
126+
btb = None,
127+
dcache = Some(DCacheParams(
128+
rowBits = site(SystemBusKey).beatBits,
129+
nSets = 256, // 16Kb scratchpad
130+
nWays = 1,
131+
nTLBSets = 1,
132+
nTLBWays = 4,
133+
nMSHRs = 0,
134+
blockBytes = site(CacheBlockBytes),
135+
scratch = Some(0x80000000L))),
136+
icache = Some(ICacheParams(
137+
rowBits = site(SystemBusKey).beatBits,
138+
nSets = 64,
139+
nWays = 1,
140+
nTLBSets = 1,
141+
nTLBWays = 4,
142+
blockBytes = site(CacheBlockBytes)))
143+
)
144+
List(RocketTileAttachParams(
145+
tiny,
146+
RocketCrossingParams(
147+
crossingType = SynchronousCrossing(),
148+
master = HierarchicalElementMasterPortParams())
149+
))
150+
}
151+
case NumTiles => 1
152+
case ClustersLocated(_) => Nil
153+
})
154+
155+
class RocketTileAttachConfig(f: RocketTileAttachParams => RocketTileAttachParams) extends TileAttachConfig[RocketTileAttachParams](f)
156+
157+
class RocketTileConfig(f: RocketTileParams => RocketTileParams) extends RocketTileAttachConfig(tp => tp.copy(
158+
tileParams = f(tp.tileParams)
159+
))
160+
161+
class RocketCrossingConfig(f: RocketCrossingParams => RocketCrossingParams) extends RocketTileAttachConfig(tp => tp.copy(
162+
crossingParams = f(tp.crossingParams)
163+
))
164+
165+
class RocketCoreConfig(f: RocketCoreParams => RocketCoreParams) extends RocketTileConfig(tp => tp.copy(
166+
core = f(tp.core)
167+
))
168+
169+
class RocketICacheConfig(f: ICacheParams => ICacheParams) extends RocketTileConfig(tp => tp.copy(
170+
icache = tp.icache.map(ic => f(ic))
171+
))
172+
173+
class RocketDCacheConfig(f: DCacheParams => DCacheParams) extends RocketTileConfig(tp => tp.copy(
174+
dcache = tp.dcache.map(dc => f(dc))
175+
))
176+
177+
class WithL1ICacheSets(sets: Int) extends RocketICacheConfig(_.copy(nSets=sets))
178+
class WithL1ICacheWays(ways: Int) extends RocketICacheConfig(_.copy(nWays=ways))
179+
class WithL1ICacheECC(dataECC: String, tagECC: String) extends RocketICacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC)))
180+
class WithL1ICacheRowBits(n: Int) extends RocketICacheConfig(_.copy(rowBits = n))
181+
class WithL1ICacheTLBSets(sets: Int) extends RocketICacheConfig(_.copy(nTLBSets = sets))
182+
class WithL1ICacheTLBWays(ways: Int) extends RocketICacheConfig(_.copy(nTLBWays = ways))
183+
class WithL1ICacheTLBBasePageSectors(sectors: Int) extends RocketICacheConfig(_.copy(nTLBBasePageSectors = sectors))
184+
class WithL1ICacheTLBSuperpages(superpages: Int) extends RocketICacheConfig(_.copy(nTLBSuperpages = superpages))
185+
class WithL1ICacheBlockBytes(bytes: Int = 64) extends RocketICacheConfig(_.copy(blockBytes = bytes))
186+
187+
class WithL1DCacheSets(sets: Int) extends RocketDCacheConfig(_.copy(nSets=sets))
188+
class WithL1DCacheWays(ways: Int) extends RocketDCacheConfig(_.copy(nWays=ways))
189+
class WithL1DCacheECC(dataECC: String, tagECC: String) extends RocketDCacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC)))
190+
class WithL1DCacheRowBits(n: Int) extends RocketDCacheConfig(_.copy(rowBits = n))
191+
class WithL1DCacheTLBSets(sets: Int) extends RocketDCacheConfig(_.copy(nTLBSets = sets))
192+
class WithL1DCacheTLBWays(ways: Int) extends RocketDCacheConfig(_.copy(nTLBWays = ways))
193+
class WithL1DCacheTLBBasePageSectors(sectors: Int) extends RocketDCacheConfig(_.copy(nTLBBasePageSectors = sectors))
194+
class WithL1DCacheTLBSuperpages(superpages: Int) extends RocketDCacheConfig(_.copy(nTLBSuperpages = superpages))
195+
class WithL1DCacheBlockBytes(bytes: Int = 64) extends RocketDCacheConfig(_.copy(blockBytes = bytes))
196+
class WithL1DCacheNonblocking(nMSHRs: Int) extends RocketDCacheConfig(_.copy(nMSHRs = nMSHRs))
197+
class WithL1DCacheClockGating extends RocketDCacheConfig(_.copy(clockGate = true))
198+
class WithL1DCacheDTIMAddress(address: BigInt) extends RocketDCacheConfig(_.copy(scratch = Some(address)))
199+
200+
class WithScratchpadsOnly extends RocketTileConfig(tp => tp.copy(
201+
core = tp.core.copy(useVM = false),
202+
dcache = tp.dcache.map(_.copy(
203+
nSets = 256, // 16Kb scratchpad
204+
nWays = 1,
205+
scratch = Some(0x80000000L)))
206+
))
207+
208+
class WithCacheRowBits(n: Int) extends RocketTileConfig(tp => tp.copy(
209+
dcache = tp.dcache.map(_.copy(rowBits = n)),
210+
icache = tp.icache.map(_.copy(rowBits = n))
211+
))
212+
213+
class WithBEU(addr: BigInt) extends RocketTileConfig(_.copy(beuAddr = Some(addr)))
214+
class WithBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends RocketTileConfig(_.copy(boundaryBuffers = buffers))
215+
216+
class WithRV32 extends RocketCoreConfig(c => c.copy(
217+
xLen = 32,
218+
pgLevels = 2, // sv32
219+
fpu = c.fpu.map(_.copy(fLen = 32)),
220+
mulDiv = Some(MulDivParams(mulUnroll = 8))
221+
))
222+
223+
class WithoutVM extends RocketCoreConfig(_.copy(useVM = false))
224+
class WithCFlushEnabled extends RocketCoreConfig(_.copy(haveCFlush = true))
225+
class WithNBreakpoints(hwbp: Int) extends RocketCoreConfig(_.copy(nBreakpoints = hwbp))
226+
class WithHypervisor(hext: Boolean = true) extends RocketCoreConfig(_.copy(useHypervisor = hext))
227+
class WithCease(enable: Boolean = true) extends RocketCoreConfig(_.copy(haveCease = enable))
228+
class WithCoreClockGatingEnabled extends RocketCoreConfig(_.copy(clockGate = true))
229+
class WithPgLevels(n: Int) extends RocketCoreConfig(_.copy(pgLevels = n))
230+
class WithSV48 extends WithPgLevels(4)
231+
class WithSV39 extends WithPgLevels(3)
232+
233+
// Simulation-only configs
234+
class WithNoSimulationTimeout extends RocketCoreConfig(_.copy(haveSimTimeout = false))
235+
class WithDebugROB(enable: Boolean = true, size: Int = 0) extends RocketCoreConfig(_.copy(debugROB = Option.when(enable)(DebugROBParams(size))))
236+
237+
// FPU configs
238+
class WithoutFPU extends RocketCoreConfig(_.copy(fpu = None))
239+
class WithFP16 extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(minFLen = 16))))
240+
class WithFPUWithoutDivSqrt extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(divSqrt = false))))
241+
242+
// mul-div configs
243+
class WithFastMulDiv extends RocketCoreConfig(c => c.copy(mulDiv = Some(
244+
MulDivParams(mulUnroll = 8, mulEarlyOut = c.xLen > 32, divEarlyOut = true)
245+
)))
246+
class WithCustomFastMulDiv(mUnroll: Int = 8, mEarlyOut: Boolean = true, dUnroll: Int = 1, dEarlyOut: Boolean = true, dEarlyOutGranularity: Int = 1) extends RocketCoreConfig(_.copy(mulDiv = Some(
247+
MulDivParams(mulUnroll = mUnroll, mulEarlyOut = mEarlyOut, divUnroll = dUnroll, divEarlyOut = dEarlyOut, divEarlyOutGranularity = dEarlyOutGranularity)
248+
)))
249+
class WithoutMulDiv extends RocketCoreConfig(_.copy(mulDiv = None))
250+
251+
// Branch-prediction configs
252+
class WithDefaultBtb extends RocketTileConfig(t => t.copy(btb = Some(BTBParams())))
253+
class WithNoBtb extends RocketTileConfig(_.copy(btb = None))
254+
255+
// Tile CDC configs
256+
class WithCDC(crossingType: ClockCrossingType = SynchronousCrossing()) extends RocketCrossingConfig(_.copy(crossingType = crossingType))
257+
class WithSeperateClockReset extends RocketCrossingConfig(_.copy(forceSeparateClockReset = true))
258+
class WithSynchronousCDCs extends WithCDC(SynchronousCrossing())
259+
class WithAsynchronousCDCs(depth: Int, sync: Int) extends WithCDC(AsynchronousCrossing(depth, sync))
260+
class WithRationalCDCs extends WithCDC(RationalCrossing())
261+
262+
263+
264+
class WithCloneRocketTiles(
265+
n: Int = 1,
266+
cloneTileId: Int = 0,
267+
location: HierarchicalLocation = InSubsystem,
268+
cloneLocation: HierarchicalLocation = InSubsystem
269+
) extends Config((site, here, up) => {
270+
case TilesLocated(`location`) => {
271+
val prev = up(TilesLocated(location), site)
272+
val idOffset = up(NumTiles)
273+
val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId)
274+
.get.asInstanceOf[RocketTileAttachParams]
275+
(0 until n).map { i =>
276+
CloneTileAttachParams(cloneTileId, tileAttachParams.copy(
277+
tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset)
278+
))
279+
} ++ prev
280+
}
281+
case NumTiles => up(NumTiles) + n
282+
})
283+

Diff for: ‎src/main/scala/rocket/RVC.scala

+2-2
Original file line numberDiff line numberDiff line change
@@ -197,12 +197,12 @@ class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) ext
197197

198198
if (usingCompressed) {
199199
io.rvc := io.in(1,0) =/= 3.U
200-
val decoder = new RVCDecoder(io.in, p(XLen), fLen, useAddiForMv)
200+
val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv)
201201
io.out := decoder.decode
202202
io.ill := decoder.ill
203203
} else {
204204
io.rvc := false.B
205-
io.out := new RVCDecoder(io.in, p(XLen), fLen, useAddiForMv).passthrough
205+
io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough
206206
io.ill := false.B // only used for RVC
207207
}
208208
}

Diff for: ‎src/main/scala/rocket/RocketCore.scala

+2
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@ import freechips.rocketchip.util.property
1313
import scala.collection.mutable.ArrayBuffer
1414

1515
case class RocketCoreParams(
16+
xLen: Int = 64,
17+
pgLevels: Int = 3, // sv39 default
1618
bootFreqHz: BigInt = 0,
1719
useVM: Boolean = true,
1820
useUser: Boolean = false,

Diff for: ‎src/main/scala/rocket/TLB.scala

-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@ import freechips.rocketchip.util.UIntIsOneOf
2323
import freechips.rocketchip.util.SeqToAugmentedSeq
2424
import freechips.rocketchip.util.SeqBoolBitwiseOps
2525

26-
case object PgLevels extends Field[Int](2)
2726
case object ASIdBits extends Field[Int](0)
2827
case object VMIdBits extends Field[Int](0)
2928

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