diff --git a/src/main/scala/subsystem/Ports.scala b/src/main/scala/subsystem/Ports.scala
index d3ed70c5e9..7a9fda1ca8 100644
--- a/src/main/scala/subsystem/Ports.scala
+++ b/src/main/scala/subsystem/Ports.scala
@@ -105,8 +105,9 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem =>
     })
 
     mbus.coupleTo(s"memory_controller_port_named_$portName") {
-      (memAXI4Node
-        := AXI4UserYanker()
+      // Disable monitors on this connection since the class with this trait (i.e. DigitalTop) doesn't provide an
+      // implicit clock for the monitor.
+      (DisableMonitors { implicit p => memAXI4Node := AXI4UserYanker() }
         := AXI4IdIndexer(idBits)
         := TLToAXI4()
         := TLWidthWidget(mbus.beatBytes)