common.mill

// SPDX-License-Identifier: Apache-2.0
// SPDX-FileCopyrightText: 2022 Jiuyang Liu <liu@jiuyang.me>

package build

import mill._
import mill.scalalib._

trait HasChisel extends ScalaModule {
  // Define these for building chisel from source
  def chiselModule: Option[ScalaModule]

  override def moduleDeps = super.moduleDeps ++ chiselModule

  def chiselPluginJar: T[Option[PathRef]]

  override def scalacOptions = T(
    super.scalacOptions() ++ chiselPluginJar().map(path => s"-Xplugin:${path.path}") ++ Seq("-Ymacro-annotations")
  )

  override def scalacPluginClasspath: T[Agg[PathRef]] = T(super.scalacPluginClasspath() ++ chiselPluginJar())

  // Define these for building chisel from ivy
  def chiselIvy: Option[Dep]

  override def ivyDeps = T(super.ivyDeps() ++ chiselIvy)

  def chiselPluginIvy: Option[Dep]

  override def scalacPluginIvyDeps: T[Agg[Dep]] = T(
    super.scalacPluginIvyDeps() ++ chiselPluginIvy.map(Agg(_)).getOrElse(Agg.empty[Dep])
  )
}

trait HasRVDecoderDB extends ScalaModule {
  def rvdecoderdbIvy: Dep
  def riscvOpcodesPath:  T[PathRef]
  def ivyDeps = T(super.ivyDeps() ++ Seq(rvdecoderdbIvy))
  def riscvOpcodesTar:    T[PathRef]      = T {
    val tmpDir = os.temp.dir()
    os.makeDir(tmpDir / "unratified")
    os.walk(riscvOpcodesPath().path)
      .filter(f =>
        f.baseName.startsWith("rv128_") ||
          f.baseName.startsWith("rv64_") ||
          f.baseName.startsWith("rv32_") ||
          f.baseName.startsWith("rv_") ||
          f.ext == "csv"
      )
      .groupBy(_.segments.contains("unratified"))
      .map {
        case (true, fs)  => fs.map(os.copy.into(_, tmpDir / "unratified"))
        case (false, fs) => fs.map(os.copy.into(_, tmpDir))
      }
    os.proc("tar", "cf", T.dest / "riscv-opcodes.tar", ".").call(tmpDir)
    PathRef(T.dest)
  }
  override def resources: T[Seq[PathRef]] = super.resources() ++ Some(riscvOpcodesTar())
}

// Local definitions
trait T1Module extends ScalaModule with HasChisel with HasRVDecoderDB {
  def arithmeticIvy: Dep
  def hardfloatIvy:  Dep
  def axi4Ivy:       Dep
  def stdlibModule:     ScalaModule
  def moduleDeps = super.moduleDeps ++ Seq(stdlibModule)
  override def ivyDeps = T(super.ivyDeps() ++ Seq(arithmeticIvy, hardfloatIvy, axi4Ivy))
}

trait ConfigGenModule extends ScalaModule {
  def t1Module: ScalaModule
  def moduleDeps = super.moduleDeps ++ Seq(t1Module)
  def mainargsIvy: Dep
  override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
}

// T1 forked version of RocketCore
trait RocketModule extends ScalaModule with HasChisel with HasRVDecoderDB {
  def rocketchipModule: ScalaModule
  def moduleDeps = super.moduleDeps ++ Seq(rocketchipModule)
}

// The next generation of purely standalone Rocket Core w/ AXI/CHI.
trait RocketVModule extends ScalaModule with HasChisel with HasRVDecoderDB {
  def axi4Ivy:      Dep
  def hardfloatIvy: Dep
  def stdlibModule:    ScalaModule

  def moduleDeps = super.moduleDeps ++ Seq(stdlibModule)
  override def ivyDeps = T(super.ivyDeps() ++ Seq(hardfloatIvy, axi4Ivy))
}

// Link T1 example: RocketV+T1
trait T1RocketModule extends ScalaModule with HasChisel {
  def rocketModule: ScalaModule
  def t1Module:     ScalaModule

  def moduleDeps = super.moduleDeps ++ Seq(rocketModule, t1Module)
}

trait EmuHelperModule extends ScalaModule with HasChisel

trait T1EmulatorModule extends ScalaModule with HasChisel {
  def t1Module: ScalaModule
  def moduleDeps = super.moduleDeps ++ Seq(t1Module)
}

trait T1RocketEmulatorModule extends ScalaModule with HasChisel {
  def t1rocketModule: ScalaModule
  def moduleDeps = super.moduleDeps ++ Seq(t1rocketModule)
}

trait ElaboratorModule extends ScalaModule with HasChisel {
  def generators:            Seq[ScalaModule]
  def panamaconverterIvy: Dep
  def circtInstallPath:      T[PathRef]
  override def moduleDeps = super.moduleDeps ++ generators
  def mainargsIvy: Dep
  override def ivyDeps      = T(super.ivyDeps() ++ Seq(panamaconverterIvy) ++ Seq(mainargsIvy))
  override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
  override def forkArgs: T[Seq[String]] = T(
    super.forkArgs() ++ Seq(
      "--enable-native-access=ALL-UNNAMED",
      "--enable-preview",
      s"-Djava.library.path=${circtInstallPath().path / "lib"}"
    )
  )
}

trait OMReaderLibModule extends ScalaModule with HasChisel {
  def panamaconverterIvy: Dep
  def circtInstallPath:      T[PathRef]
  def mainargsIvy: Dep
  override def ivyDeps      = T(super.ivyDeps() ++ Seq(mainargsIvy, panamaconverterIvy))
  override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
  override def forkArgs: T[Seq[String]] = T(
    super.forkArgs() ++ Seq(
      "--enable-native-access=ALL-UNNAMED",
      "--enable-preview",
      s"-Djava.library.path=${circtInstallPath().path / "lib"}"
    )
  )
}

trait OMReaderModule extends ScalaModule with HasChisel {
  def panamaconverterIvy: Dep
  def omreaderlibModule:     ScalaModule
  def circtInstallPath:      T[PathRef]
  override def moduleDeps = super.moduleDeps ++ Seq(omreaderlibModule)
  def mainargsIvy: Dep
  override def ivyDeps      = T(super.ivyDeps() ++ Seq(mainargsIvy, panamaconverterIvy))
  override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
  override def forkArgs: T[Seq[String]] = T(
    super.forkArgs() ++ Seq(
      "--enable-native-access=ALL-UNNAMED",
      "--enable-preview",
      s"-Djava.library.path=${circtInstallPath().path / "lib"}"
    )
  )
}

trait StdlibModule extends ScalaModule with HasChisel {
  def dwbbIvy: Dep

  override def ivyDeps = T(super.ivyDeps() ++ Seq(dwbbIvy))
}