Skip to content

Commit

Permalink
[difftest] Format and change println!s to debug!s
Browse files Browse the repository at this point in the history
  • Loading branch information
@CircuitCoder
CircuitCoder committed Feb 21, 2025
1 parent e4bd1b1 commit 67deecb
Show file tree
Hide file tree
Showing 3 changed files with 49 additions and 48 deletions.
19 changes: 6 additions & 13 deletions difftest/dpi_t1rocketemu/src/dpi.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ use dpi_common::DpiTarget;
use std::ffi::{c_char, c_longlong, c_ulonglong};
use svdpi::dpi::param::InStr;
use svdpi::SvScope;
use tracing::error;
use tracing::{error, debug};

use crate::drive::{Driver, IncompleteRead, IncompleteWrite, OnlineArgs};

Expand Down Expand Up @@ -74,7 +74,7 @@ unsafe extern "C" fn axi_push_AW(
let w = IncompleteWrite::new(awid, awaddr, awlen, awsize, awuser, data_width);
let fifo = target.incomplete_writes.entry(channel_id).or_default();
fifo.push_back(w);
// println!("[{}] Write initialized: channel_id={} id={} at=0x{:x}", crate::get_t(), channel_id, awid, awaddr);
debug!("[{}] Write initialized: channel_id={} id={} at=0x{:x}", crate::get_t(), channel_id, awid, awaddr);
});
unsafe { ready.write(true as u8) };
}
Expand Down Expand Up @@ -102,7 +102,7 @@ unsafe extern "C" fn axi_push_AR(
let r = IncompleteRead::new(araddr, arlen, arsize, aruser, data_width);
let fifo = target.incomplete_reads.entry((channel_id, arid)).or_default();
fifo.push_back(r);
// println!("[{}] Read initialized: channel_id={} id={} at=0x{:x}", crate::get_t(), channel_id, arid, araddr);
debug!("[{}] Read initialized: channel_id={} id={} at=0x{:x}", crate::get_t(), channel_id, arid, araddr);
});
unsafe { ready.write(true as u8) };
}
Expand Down Expand Up @@ -138,7 +138,7 @@ unsafe extern "C" fn axi_push_W(
};
w.push(wslice, wstrbit, wlast != 0, data_width);
if wlast != 0 {
// println!("[{}] Write fully sequenced: channel_id={} id={}", crate::get_t(), channel_id, w.id());
debug!("[{}] Write fully sequenced: channel_id={} id={}", crate::get_t(), channel_id, w.id());
}
unsafe { ready.write(true as u8) };
})
Expand Down Expand Up @@ -169,18 +169,11 @@ unsafe extern "C" fn axi_pop_B(
None => return,
};
// TODO: find later writes with different IDs
/*
if let Some(w) = fifo.front() {
if !w.done() {
println!("[{}] Write queue head not completed: channel_id={} id={}", crate::get_t(), channel_id, w.id());
}
}
*/
if fifo.front().as_ref().is_none_or(|w| !w.done()) {
return;
}
let w = fifo.pop_front().unwrap();
// println!("[{}] Write finalized: channel_id={} id={}", crate::get_t(), channel_id, w.id());
debug!("[{}] Write finalized: channel_id={} id={}", crate::get_t(), channel_id, w.id());
unsafe {
ret.write(1);
(ret.offset(2) as *mut u16).write(w.id() as u16);
Expand Down Expand Up @@ -229,7 +222,7 @@ unsafe extern "C" fn axi_pop_R(
}

if last {
// println!("[{}] Read finalized: channel_id={} id={}", crate::get_t(), channel_id, *id);
debug!("[{}] Read finalized: channel_id={} id={}", crate::get_t(), channel_id, *id);
fifo.pop_front();
}
return;
Expand Down
7 changes: 4 additions & 3 deletions difftest/dpi_t1rocketemu/src/interconnect.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ use std::{
rc::Rc,
sync::{Arc, Mutex},
};
use tracing::debug;

use framebuffer::FrameBuffer;
use simctrl::{ExitFlagRef, SimCtrl};
Expand Down Expand Up @@ -226,11 +227,11 @@ impl DRAMModel {
let ds_path_cstr =
CString::new(ds_path.as_ref().as_os_str().as_bytes()).expect("Incorrect path format");
let sys = dramsim3::MemorySystem::new(&ds_cfg_cstr, &ds_path_cstr, move |addr, is_write| {
// println!("DRAM Memory response: {:x}, write={}", addr, is_write);
debug!("DRAM Memory response: {:x}, write={}", addr, is_write);
for req in inflights_clone.lock().unwrap().iter_mut() {
if !req.done() && req.done_ptr as u64 == addr && req.is_write == is_write {
// TODO: pass chunk_size from dramsim3
// println!("Found req: id={:x}", req.id);
debug!("Found req: id={:x}", req.id);
req.done_ptr += chunk_size.get();
return;
}
Expand Down Expand Up @@ -259,7 +260,7 @@ impl DRAMModel {
impl MemoryModel for DRAMModel {
fn push(&mut self, req: MemIdent) {
// TODO: done if in cache
// println!("DRAM Pushing: {:x}, size = {}", req.req.offset, req.req.len);
debug!("DRAM Pushing: {:x}, size = {}", req.req.offset, req.req.len);
self.inflights.lock().unwrap().push(InflightMem::from_ident(req, self.req_size()));
}

Expand Down
71 changes: 39 additions & 32 deletions t1rocketemu/src/AXI4SlaveAgent.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,25 +9,32 @@ import chisel3.util.circt.dpi.{RawClockedNonVoidFunctionCall, RawClockedVoidFunc
import chisel3.util.{isPow2, log2Ceil, Queue}
import chisel3.experimental.dataview._
import org.chipsalliance.amba.axi4.bundle.{
AR, AW, R, W, B,
HasAR, HasAW, HasR, HasW, HasB,
AXI4ChiselBundle,
AXI4ROIrrevocable,
AXI4RWIrrevocable,
AXI4WOIrrevocable,

AR,
ARChannel,
ARFlowControl,
AW,
AWChannel,
AWFlowControl,
AXI4BundleParameter,
AXI4ChiselBundle,
AXI4ROIrrevocable,
AXI4ROIrrevocableVerilog,
AXI4RWIrrevocable,
AXI4RWIrrevocableVerilog,
AXI4WOIrrevocable,
AXI4WOIrrevocableVerilog,
B,
BChannel,
BFlowControl,
HasAR,
HasAW,
HasB,
HasR,
HasW,
R,
RChannel,
RFlowControl,
W,
WChannel,
WFlowControl
}
Expand Down Expand Up @@ -69,28 +76,28 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
val invClock = (~io.clock.asBool).asClock;

io.channel match {
case channel : AXI4RWIrrevocableVerilog => {
case channel: AXI4RWIrrevocableVerilog => {
val view = channel.viewAs[AXI4RWIrrevocable](
implicitly,
AXI4RWIrrevocableVerilog.viewChisel,
implicitly,
implicitly
)
new ReadManager(view)
new WriteManager(view)
}
case channel : AXI4ROIrrevocableVerilog => {
case channel: AXI4ROIrrevocableVerilog => {
val view = channel.viewAs[AXI4ROIrrevocable](
implicitly,
AXI4ROIrrevocableVerilog.viewChisel,
implicitly,
implicitly
)
new ReadManager(view)
}
case channel : AXI4WOIrrevocableVerilog => {
case channel: AXI4WOIrrevocableVerilog => {
val view = channel.viewAs[AXI4WOIrrevocable](
implicitly,
AXI4WOIrrevocableVerilog.viewChisel,
implicitly,
implicitly
)
new WriteManager(view)
}
Expand All @@ -99,7 +106,7 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
RawClockedVoidFunctionCall(s"axi_tick")(
io.clock,
true.B,
io.reset.asTypeOf(UInt(8.W)),
io.reset.asTypeOf(UInt(8.W))
)

/// Widen a wire to make all DPI calls' types uniform
Expand All @@ -112,8 +119,8 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
private class WriteManager(channel: HasAW with HasW with HasB) {
withClockAndReset(io.clock, io.reset) {
val awqueue = Module(new Queue(new AW(parameter.axiParameter), 2))
val wqueue = Module(new Queue(new W(parameter.axiParameter), 2))
val bqueue = Module(new Queue(new B(parameter.axiParameter), 2))
val wqueue = Module(new Queue(new W(parameter.axiParameter), 2))
val bqueue = Module(new Queue(new B(parameter.axiParameter), 2))

awqueue.io.enq <> channel.aw
wqueue.io.enq <> channel.w
Expand All @@ -133,7 +140,7 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
awqueue.io.deq.bits.addr.asTypeOf(UInt(64.W)),
awqueue.io.deq.bits.size.asTypeOf(UInt(64.W)),
awqueue.io.deq.bits.len.asTypeOf(UInt(64.W)),
awqueue.io.deq.bits.user.asTypeOf(UInt(64.W)),
awqueue.io.deq.bits.user.asTypeOf(UInt(64.W))
)
awqueue.io.deq.ready := awRet

Expand All @@ -146,26 +153,26 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
parameter.axiParameter.dataWidth.U(64.W),
widen(wqueue.io.deq.bits.data, 1024),
widen(wqueue.io.deq.bits.strb, 128),
wqueue.io.deq.bits.last.asTypeOf(UInt(8.W)),
wqueue.io.deq.bits.last.asTypeOf(UInt(8.W))
)
wqueue.io.deq.ready := wRet

class BBundle extends Bundle {
val user = UInt(32.W)
val id = UInt(16.W)
val user = UInt(32.W)
val id = UInt(16.W)
val _padding = UInt(8.W)
val valid = UInt(8.W)
val valid = UInt(8.W)
}

val bRet = RawClockedNonVoidFunctionCall(s"axi_pop_B", new BBundle())(
invClock,
bqueue.io.enq.ready,
io.reset.asTypeOf(UInt(64.W)),
io.channelId,
parameter.axiParameter.dataWidth.U(64.W),
parameter.axiParameter.dataWidth.U(64.W)
)
bqueue.io.enq.valid := bRet.valid
bqueue.io.enq.bits.id := bRet.id
bqueue.io.enq.valid := bRet.valid
bqueue.io.enq.bits.id := bRet.id
bqueue.io.enq.bits.resp := 0.U(2.W)
bqueue.io.enq.bits.user := bRet.user
}
Expand All @@ -175,7 +182,7 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
private class ReadManager(channel: HasAR with HasR) {
withClockAndReset(io.clock, io.reset) {
val arqueue = Module(new Queue(new AR(parameter.axiParameter), 2))
val rqueue = Module(new Queue(new R(parameter.axiParameter), 2))
val rqueue = Module(new Queue(new R(parameter.axiParameter), 2))

arqueue.io.enq <> channel.ar
rqueue.io.deq <> channel.r
Expand All @@ -191,27 +198,27 @@ class AXI4SlaveAgent(parameter: AXI4SlaveAgentParameter)
arqueue.io.deq.bits.addr.asTypeOf(UInt(64.W)),
arqueue.io.deq.bits.size.asTypeOf(UInt(64.W)),
arqueue.io.deq.bits.len.asTypeOf(UInt(64.W)),
arqueue.io.deq.bits.user.asTypeOf(UInt(64.W)),
arqueue.io.deq.bits.user.asTypeOf(UInt(64.W))
)
arqueue.io.deq.ready := arRet

require(parameter.axiParameter.dataWidth <= 1024)
class RBundle extends Bundle {
val data = UInt(1024.W)
val data = UInt(1024.W)
val user = UInt(32.W)
val id = UInt(16.W)
val last = UInt(8.W)
val id = UInt(16.W)
val last = UInt(8.W)
val valid = UInt(8.W)
}
val rRet = RawClockedNonVoidFunctionCall(s"axi_pop_R", new RBundle())(
invClock,
rqueue.io.enq.ready,
io.reset.asTypeOf(UInt(8.W)),
io.channelId,
parameter.axiParameter.dataWidth.U(64.W),
parameter.axiParameter.dataWidth.U(64.W)
)
rqueue.io.enq.valid := rRet.valid
rqueue.io.enq.bits.id := rRet.id
rqueue.io.enq.valid := rRet.valid
rqueue.io.enq.bits.id := rRet.id
rqueue.io.enq.bits.last := rRet.last
rqueue.io.enq.bits.user := rRet.user
rqueue.io.enq.bits.data := rRet.data
Expand Down

0 comments on commit 67deecb

Please sign in to comment.