[rtl] fix accessBufferDequeueReady in store unit(&addressQueueFree).

chipsalliance · Feb 26, 2025 · 6fee110 · 6fee110
1 parent 9de2f4c
commit 6fee110
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/t1/src/lsu/StoreUnit.scala b/t1/src/lsu/StoreUnit.scala
@@ -167,7 +167,8 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
   val canSendTail:               Bool      = RegInit(false.B)
   val isLastCacheLineInBuffer:   Bool      = cacheLineIndexInBuffer === lsuRequestReg.instructionInformation.nf
   val bufferWillClear:           Bool      = alignedDequeueFire && isLastCacheLineInBuffer
-  accessBufferDequeueReady := !bufferValid || (memRequest.ready && isLastCacheLineInBuffer)
+  val addressQueueFree:          Bool      = Wire(Bool())
+  accessBufferDequeueReady := !bufferValid || (memRequest.ready && isLastCacheLineInBuffer && addressQueueFree)
   val bufferStageEnqueueData: Vec[UInt] = Mux(bufferFull, accessData, accessDataUpdate)
   // 处理mask, 对于 segment type 来说 一个mask 管 nf 个element
   val fillBySeg:              UInt      = Mux1H(
@@ -248,8 +249,7 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
   }
 
   // 连接 alignedDequeue
-  val needSendTail:     Bool = bufferBaseCacheLineIndex === cacheLineNumberReg
-  val addressQueueFree: Bool = Wire(Bool())
+  val needSendTail: Bool = bufferBaseCacheLineIndex === cacheLineNumberReg
   memRequest.valid     := (bufferValid || (canSendTail && needSendTail)) && addressQueueFree
   // aligned
   memRequest.bits.data :=