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[spike] remove all varch specification
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Latest version of spike support reading VLEN,ELEN from ISA now.

Signed-off-by: Avimitin <dev@avimit.in>
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Avimitin committed Jul 27, 2024
1 parent c091ac3 commit cd00f75
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Showing 4 changed files with 9 additions and 14 deletions.
11 changes: 5 additions & 6 deletions difftest/spike_interfaces/spike_interfaces.cc
Original file line number Diff line number Diff line change
Expand Up @@ -6,13 +6,12 @@ constexpr uint32_t CSR_MSIMEND = 0x7cc;

void *ffi_target;

cfg_t make_spike_cfg(const std::string &varch) {
cfg_t make_spike_cfg() {
cfg_t cfg;
cfg.initrd_bounds = std::make_pair((reg_t)0, (reg_t)0),
cfg.bootargs = nullptr;
cfg.isa = DEFAULT_ISA;
cfg.priv = DEFAULT_PRIV;
cfg.varch = varch.data();
cfg.misaligned = false;
cfg.endianness = endianness_little;
cfg.pmpregions = 16;
Expand All @@ -25,9 +24,9 @@ cfg_t make_spike_cfg(const std::string &varch) {
return cfg;
}

Spike::Spike(const char *arch, const char *set, const char *lvl,
Spike::Spike(const char *set, const char *lvl,
size_t lane_number)
: sim(), varch(arch), isa(set, lvl), cfg(make_spike_cfg(varch)),
: sim(), isa(set, lvl), cfg(make_spike_cfg()),
proc(
/*isa*/ &isa,
/*cfg*/ &cfg,
Expand All @@ -44,9 +43,9 @@ Spike::Spike(const char *arch, const char *set, const char *lvl,
proc.enable_log_commits();
}

spike_t *spike_new(const char *arch, const char *set, const char *lvl,
spike_t *spike_new(const char *set, const char *lvl,
size_t lane_number) {
return new spike_t{new Spike(arch, set, lvl, lane_number)};
return new spike_t{new Spike(set, lvl, lane_number)};
}

const char *proc_disassemble(spike_processor_t *proc) {
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3 changes: 1 addition & 2 deletions difftest/spike_interfaces/spike_interfaces.h
Original file line number Diff line number Diff line change
Expand Up @@ -45,11 +45,10 @@ class sim_t : public simif_t {

class Spike {
public:
Spike(const char *arch, const char *set, const char *lvl, size_t lane_number);
Spike(const char *set, const char *lvl, size_t lane_number);
processor_t *get_proc() { return &proc; }

private:
std::string varch;
cfg_t cfg;
sim_t sim;
isa_parser_t isa;
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6 changes: 2 additions & 4 deletions difftest/spike_rs/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -38,11 +38,10 @@ type FfiCallback = extern "C" fn(*mut (), u64) -> *mut u8;

impl Spike {
// we need to have a boxed SpikeCObject, since its pointer will be passed to C to perform FFI call
pub fn new(arch: &str, set: &str, lvl: &str, lane_number: usize, mem_size: usize) -> Box<Self> {
let arch = CString::new(arch).unwrap();
pub fn new(set: &str, lvl: &str, lane_number: usize, mem_size: usize) -> Box<Self> {
let set = CString::new(set).unwrap();
let lvl = CString::new(lvl).unwrap();
let spike = unsafe { spike_new(arch.as_ptr(), set.as_ptr(), lvl.as_ptr(), lane_number) };
let spike = unsafe { spike_new(set.as_ptr(), lvl.as_ptr(), lane_number) };
let mut self_: Box<Spike> = Box::new(Spike { spike, mem: vec![0; mem_size], size: mem_size });

// TODO: support customized ffi
Expand Down Expand Up @@ -243,7 +242,6 @@ impl Drop for State {
extern "C" {
pub fn spike_register_callback(target: *mut (), callback: FfiCallback);
fn spike_new(
arch: *const c_char,
set: *const c_char,
lvl: *const c_char,
lane_number: usize,
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3 changes: 1 addition & 2 deletions difftest/test_common/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -40,10 +40,9 @@ pub static MEM_SIZE: usize = 1usize << 32;

impl CommonArgs {
pub fn to_spike_c_handler(&self) -> Box<Spike> {
let arch = &format!("vlen:{},elen:32", self.vlen);
let lvl = "M";

Spike::new(arch, &self.set, lvl, (self.dlen / 32) as usize, MEM_SIZE)
Spike::new(&self.set, lvl, (self.dlen / 32) as usize, MEM_SIZE)
}

pub fn setup_logger(&self) -> Result<()> {
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