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jhart99 opened this issue Mar 25, 2025 · 2 comments
Open

[RISC-V] OrangePi RV2 preliminary results #536

jhart99 opened this issue Mar 25, 2025 · 2 comments

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@jhart99
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jhart99 commented Mar 25, 2025 

Processor                                                                     []
|- Architecture                                                       [SpacemiT]
|- Vendor ID                                                          [SpacemiT]
|- Revision                                                         [0x00000000]
|- Signature                                                           [ 710_00]
|- Stepping                                                            [   r0p0]
|- Online CPU                                                          [  8/  8]
|- Base Clock                                                          [240.003]
|- Frequency            (MHz)                      Ratio                        
                 Min   1474.58                    <   6 >                       
                 Max   3840.04                    <  16 >                       
|- Factory                                                             [100.000]
                       1004                       [  10 ]                       
|- Performance                                                                  
                 TGT   3840.04                    <  16 >                       
|- Turbo                                                               [   LOCK]
                 TBH   4320.05                    [  18 ]                       
|- OPP                                                                          
                  1C   4320.05                    <  18 >                       
                  2C   3840.04                    <  16 >                       
                  3C   2949.15                    <  12 >                       
                  4C   2400.03                    <  10 >                       
                  5C   1965.62                    <   8 >                       
|- Hybrid                                                              [   LOCK]
                  1C   4320.05                    <  18 >                       
                  2C   3840.04                    <  16 >                       
                  3C   2949.15                    <  12 >                       
                  4C   2400.03                    <  10 >                       
                  5C   1965.62                    <   8 >                       
|- Uncore                                                              [   LOCK]
                                                                                
Instruction Set Extensions                                                      
|-          AES [N]        ASIMD [N]        ATS1A [N]         BF16 [N]
|-       CLRBHB [N]  CONSTPACFLD [N]          CPA [N]        CRC32 [N]
|-         CSSC [N]          DGH [N]           DP [N]          DPB [N]
|-         DPB2 [N]        EBF16 [N]         EPAC [N]     FAMINMAX [N]
|-         FCMA [N]          FHM [N]        FlagM [N]       FlagM2 [N]
|-           FP [N]         FPAC [N]  FPACCOMBINE [N]     FP_ROUND [N]
|-    FP_Sh_Vec [N]      FP_SQRT [N]    FP_DIVIDE [N]      FP_TRAP [N]
|-        FP_DP [N]        FP_SP [N]        FP_HP [N]       FP_NaN [N]
|-       FP_FtZ [N]      FP_MISC [N]       FPRCVT [N]      FRINTTS [N]
|-          HBC [N]         I8MM [N]        JSCVT [N]        LRCPC [N]
|-       LRCPC2 [N]       LRCPC3 [N]         LS64 [N]       LS64_V [N]
|- LS64_ACCDATA [N]          LSE [N]       LSE128 [N]         LSFE [N]
|-         LSUI [N]          LUT [N]         MOPS [N]        OCCMO [N]
|-        PACGA [N]    PACQARMA3 [N]    PACQARMA5 [N]        PAuth [N]
|-       PAuth2 [N]     PAuth_LR [N]         PACM [N]     PCDPHINT [N]
|-      PRFMSLC [N]        PMULL [N]         RAND [N]         RDMA [N]
|-     RNG-TRAP [N]        RPRES [N]        RPRFM [N]           SB [N]
|-         SHA1 [N]       SHA256 [N]       SHA512 [N]         SHA3 [N]
|-     SIMD_REG [N]     SIMD_FMA [N]      SIMD_HP [N]      SIMD_SP [N]
|-     SIMD_INT [N]      SIMD_LS [N]    SIMD_MISC [N]          SM3 [N]
|-          SM4 [N]          SME [N]         SME2 [N]       SME2p1 [N]
|-     SME_FA64 [N]    SME_LUTv2 [N]   SME_I16I64 [N]   SME_F64F64 [N]
|-   SME_I16I32 [N]   SME_B16B16 [N]   SME_F16F16 [N]    SME_F8F16 [N]
|-    SME_F8F32 [N]    SME_I8I32 [N]   SME_F16F32 [N]   SME_B16F32 [N]
|-  SME_BI32I32 [N]   SME_F32F32 [N]   SME_SF8FMA [N]   SME_SF8DP4 [N]
|-   SME_SF8DP2 [N]      SPECRES [N]     SPECRES2 [N]          SVE [N]
|-         SVE2 [N]    SVE_F64MM [N]    SVE_F32MM [N]     SVE_I8MM [N]
|-      SVE_SM4 [N]     SVE_SHA3 [N]     SVE_BF16 [N]    SVE_EBF16 [N]
|-  SVE_BitPerm [N]      SVE_AES [N] SVE_PMULL128 [N]    SYSREG128 [N]
|-  SYSINSTR128 [N]        TLBIW [N]         WFxT [N]           XS [N]
                                                                                
Features                                                                        
|- Advanced Configuration & Power Interface                     ACPI   [Missing]
|- Activity Monitor Unit                                         AMU   [Missing]
|- Mixed-Endianness EL0                                       BigEnd   [Missing]
|- Mixed-Endianness EE|E0E                                    BigEnd   [Missing]
|- Exception-based event profiling                              EBEP   [Missing]
|- Enhanced Counter Virtualization                               ECV   [Missing]
|- Double Fault Extension                                        DF2   [Missing]
|- Data Independent Timing                                       DIT   [Missing]
|- Context Synchronization & Exception Handling                  ExS   [Missing]
|- Fine-Grained Trap controls                                    FGT   [Missing]
|- Fine-Grained Trap controls                                   FGT2   [Missing]
|- Floating-point Mode Register                                 FPMR   [Missing]
|- Physical Fault Address Registers                             PFAR   [Missing]
|- Generic Interrupt Controller                                  GIC   [Missing]
|- Memory Partitioning and Monitoring                           MPAM   [Missing]
|- Memory Tagging Extension                                      MTE   [Missing]
   |- Reporting Tag Check Fault                           TAGGED_FAR   [Missing]
   |- Allocation tag access permissions                         PERM   [Missing]
   |- Store-only Tag checking                              STOREONLY   [Missing]
|- Non Maskable Interrupt                                        NMI   [Missing]
|- Physical Address range 32 bits, 4GB                            PA   [Capable]
|- Privileged Access Never                                       PAN   [Missing]
|- Reliability Availability & Serviceability                     RAS   [Missing]
|- TLB maintenance instructions                               TLBIOS   [Missing]
|- TLB maintenance instructions                            TLBIRANGE   [Missing]
|- Transactional Memory Extension                                TME   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- User Access Override                                          UAO   [Missing]
|- Injection of Undefined Instruction                           UINJ   [Missing]
|- Virtual Address range 48 bits                                  VA   [Capable]
|- Virtualization Host Extensions                                VHE   [Missing]
Mitigation mechanisms                                                           
|- Clear Branch History instruction                           CLRBHB   [ Unable]
|- Speculative Store Bypass Disable                             NONE   [ Unable]
|- Speculative Store Bypass Disable                             CSV3   [ Unable]
|- Exploitative Control w/ Branch History Buffer               ECBHB   [ Unable]
|- Speculative Store Bypass Safe                                SSBS   [ Unable]
Security Features                                                               
|- Branch Target Identification                                  BTI   [Missing]
|- Guarded Control Stack                                         GCS   [Missing]
|- Realm Management Extension                                    RME   [Missing]
|- Secure EL2 Implementation                                    SEL2   [Missing]
|- Translation Hardening Extension                               THE   [Missing]
                                                                                
Technologies                                                                    
|- Instruction Cache Unit                                             I$   [OFF]
|- Data Cache Unit                                                    D$   [OFF]
|- Memory Management Unit                                            MMU   [OFF]
|- Simultaneous Multithreading                                       SMT   [OFF]
|- big.LITTLE technology                                          HYBRID   [ ON]
|- Core C-States                                                     CCx   [OFF]
|- Virtualization                                                    VHE   [OFF]
   |- I/O MMU                                                      IOMMU   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [N/A]
|- Counters:          General                   Fixed                           
|           {  0,  0,  0 } x 64 bits            3 x 64 bits                     
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x0   ]
|- ACPI Processor C-States                                      _CST   [Missing]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     0     0     0     0     0     0     0              
|- Core Cycles Counter                                                 [Missing]
|- Instructions Counter                                                [Missing]
|- Processor Performance Control                                _PCT   [Missing]
|- Performance Supported States                                 _PSS   [Missing]
|- Performance Present Capabilities                             _PPC   [Missing]
|- Continuous Performance Control                               _CPC   [ Enable]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:  0 C>
|- Digital Thermal Sensor                                        DTS   [Missing]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
|- Units                                                                        
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [      Missing]
   |- Window                                            second   [      Missing]

CPU Pkg  Main  Core/Thread  Caches      (w)rite-Barocessor                                                                     []
|- Architecture                                                       [SpacemiT]
|- Vendor ID                                                          [SpacemiT]
|- Revision                                                         [0x00000000]
|- Signature                                                           [ 710_00]
|- Stepping                                                            [   r0p0]
|- Online CPU                                                          [  8/  8]
|- Base Clock                                                          [240.003]
|- Frequency            (MHz)                      Ratio                        
                 Min   1474.58                    <   6 >                       
                 Max   3840.04                    <  16 >                       
|- Factory                                                             [100.000]
                       1004                       [  10 ]                       
|- Performance                                                                  
                 TGT   3840.04                    <  16 >                       
|- Turbo                                                               [   LOCK]
                 TBH   4320.05                    [  18 ]                       
|- OPP                                                                          
                  1C   4320.05                    <  18 >                       
                  2C   3840.04                    <  16 >                       
                  3C   2949.15                    <  12 >                       
                  4C   2400.03                    <  10 >                       
                  5C   1965.62                    <   8 >                       
|- Hybrid                                                              [   LOCK]
                  1C   4320.05                    <  18 >                       
                  2C   3840.04                    <  16 >                       
                  3C   2949.15                    <  12 >                       
                  4C   2400.03                    <  10 >                       
                  5C   1965.62                    <   8 >                       
|- Uncore                                                              [   LOCK]
                                                                                
Instruction Set Extensions                                                      
|-          AES [N]        ASIMD [N]        ATS1A [N]         BF16 [N]
|-       CLRBHB [N]  CONSTPACFLD [N]          CPA [N]        CRC32 [N]
|-         CSSC [N]          DGH [N]           DP [N]          DPB [N]
|-         DPB2 [N]        EBF16 [N]         EPAC [N]     FAMINMAX [N]
|-         FCMA [N]          FHM [N]        FlagM [N]       FlagM2 [N]
|-           FP [N]         FPAC [N]  FPACCOMBINE [N]     FP_ROUND [N]
|-    FP_Sh_Vec [N]      FP_SQRT [N]    FP_DIVIDE [N]      FP_TRAP [N]
|-        FP_DP [N]        FP_SP [N]        FP_HP [N]       FP_NaN [N]
|-       FP_FtZ [N]      FP_MISC [N]       FPRCVT [N]      FRINTTS [N]
|-          HBC [N]         I8MM [N]        JSCVT [N]        LRCPC [N]
|-       LRCPC2 [N]       LRCPC3 [N]         LS64 [N]       LS64_V [N]
|- LS64_ACCDATA [N]          LSE [N]       LSE128 [N]         LSFE [N]
|-         LSUI [N]          LUT [N]         MOPS [N]        OCCMO [N]
|-        PACGA [N]    PACQARMA3 [N]    PACQARMA5 [N]        PAuth [N]
|-       PAuth2 [N]     PAuth_LR [N]         PACM [N]     PCDPHINT [N]
|-      PRFMSLC [N]        PMULL [N]         RAND [N]         RDMA [N]
|-     RNG-TRAP [N]        RPRES [N]        RPRFM [N]           SB [N]
|-         SHA1 [N]       SHA256 [N]       SHA512 [N]         SHA3 [N]
|-     SIMD_REG [N]     SIMD_FMA [N]      SIMD_HP [N]      SIMD_SP [N]
|-     SIMD_INT [N]      SIMD_LS [N]    SIMD_MISC [N]          SM3 [N]
|-          SM4 [N]          SME [N]         SME2 [N]       SME2p1 [N]
|-     SME_FA64 [N]    SME_LUTv2 [N]   SME_I16I64 [N]   SME_F64F64 [N]
|-   SME_I16I32 [N]   SME_B16B16 [N]   SME_F16F16 [N]    SME_F8F16 [N]
|-    SME_F8F32 [N]    SME_I8I32 [N]   SME_F16F32 [N]   SME_B16F32 [N]
|-  SME_BI32I32 [N]   SME_F32F32 [N]   SME_SF8FMA [N]   SME_SF8DP4 [N]
|-   SME_SF8DP2 [N]      SPECRES [N]     SPECRES2 [N]          SVE [N]
|-         SVE2 [N]    SVE_F64MM [N]    SVE_F32MM [N]     SVE_I8MM [N]
|-      SVE_SM4 [N]     SVE_SHA3 [N]     SVE_BF16 [N]    SVE_EBF16 [N]
|-  SVE_BitPerm [N]      SVE_AES [N] SVE_PMULL128 [N]    SYSREG128 [N]
|-  SYSINSTR128 [N]        TLBIW [N]         WFxT [N]           XS [N]
                                                                                
Features                                                                        
|- Advanced Configuration & Power Interface                     ACPI   [Missing]
|- Activity Monitor Unit                                         AMU   [Missing]
|- Mixed-Endianness EL0                                       BigEnd   [Missing]
|- Mixed-Endianness EE|E0E                                    BigEnd   [Missing]
|- Exception-based event profiling                              EBEP   [Missing]
|- Enhanced Counter Virtualization                               ECV   [Missing]
|- Double Fault Extension                                        DF2   [Missing]
|- Data Independent Timing                                       DIT   [Missing]
|- Context Synchronization & Exception Handling                  ExS   [Missing]
|- Fine-Grained Trap controls                                    FGT   [Missing]
|- Fine-Grained Trap controls                                   FGT2   [Missing]
|- Floating-point Mode Register                                 FPMR   [Missing]
|- Physical Fault Address Registers                             PFAR   [Missing]
|- Generic Interrupt Controller                                  GIC   [Missing]
|- Memory Partitioning and Monitoring                           MPAM   [Missing]
|- Memory Tagging Extension                                      MTE   [Missing]
   |- Reporting Tag Check Fault                           TAGGED_FAR   [Missing]
   |- Allocation tag access permissions                         PERM   [Missing]
   |- Store-only Tag checking                              STOREONLY   [Missing]
|- Non Maskable Interrupt                                        NMI   [Missing]
|- Physical Address range 32 bits, 4GB                            PA   [Capable]
|- Privileged Access Never                                       PAN   [Missing]
|- Reliability Availability & Serviceability                     RAS   [Missing]
|- TLB maintenance instructions                               TLBIOS   [Missing]
|- TLB maintenance instructions                            TLBIRANGE   [Missing]
|- Transactional Memory Extension                                TME   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- User Access Override                                          UAO   [Missing]
|- Injection of Undefined Instruction                           UINJ   [Missing]
|- Virtual Address range 48 bits                                  VA   [Capable]
|- Virtualization Host Extensions                                VHE   [Missing]
Mitigation mechanisms                                                           
|- Clear Branch History instruction                           CLRBHB   [ Unable]
|- Speculative Store Bypass Disable                             NONE   [ Unable]
|- Speculative Store Bypass Disable                             CSV3   [ Unable]
|- Exploitative Control w/ Branch History Buffer               ECBHB   [ Unable]
|- Speculative Store Bypass Safe                                SSBS   [ Unable]
Security Features                                                               
|- Branch Target Identification                                  BTI   [Missing]
|- Guarded Control Stack                                         GCS   [Missing]
|- Realm Management Extension                                    RME   [Missing]
|- Secure EL2 Implementation                                    SEL2   [Missing]
|- Translation Hardening Extension                               THE   [Missing]
                                                                                
Technologies                                                                    
|- Instruction Cache Unit                                             I$   [OFF]
|- Data Cache Unit                                                    D$   [OFF]
|- Memory Management Unit                                            MMU   [OFF]
|- Simultaneous Multithreading                                       SMT   [OFF]
|- big.LITTLE technology                                          HYBRID   [ ON]
|- Core C-States                                                     CCx   [OFF]
|- Virtualization                                                    VHE   [OFF]
   |- I/O MMU                                                      IOMMU   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [N/A]
|- Counters:          General                   Fixed                           
|           {  0,  0,  0 } x 64 bits            3 x 64 bits                     
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x0   ]
|- ACPI Processor C-States                                      _CST   [Missing]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     0     0     0     0     0     0     0              
|- Core Cycles Counter                                                 [Missing]
|- Instructions Counter                                                [Missing]
|- Processor Performance Control                                _PCT   [Missing]
|- Performance Supported States                                 _PSS   [Missing]
|- Performance Present Capabilities                             _PPC   [Missing]
|- Continuous Performance Control                               _CPC   [ Enable]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:  0 C>
|- Digital Thermal Sensor                                        DTS   [Missing]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
|- Units                                                                        
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [      Missing]
   |- Window                                            second   [      Missing]

CPU Pkg  Main  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID  Hybrid ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000: -1    1  P   0   0 -1       0  0         0  0         0  0         0  0  
001: -1    1  P   0   1 -1       0  0         0  0         0  0         0  0  
002: -1    1  P   0   2 -1       0  0         0  0         0  0         0  0  
003: -1    1  P   0   3 -1       0  0         0  0         0  0         0  0  
004: -1    1  P   0   4 -1       0  0         0  0         0  0         0  0  
005: -1    1  P   0   5 -1       0  0         0  0         0  0         0  0  
006: -1    1  P   0   6 -1       0  0         0  0         0  0         0  0  
007: -1    1  P   0   7 -1       0  0         0  0         0  0         0  0 ck (i)nclusive              
 #   ID   ID  Hybrid ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000: -1    1  P   0   0 -1       0  0         0  0         0  0         0  0  
001: -1    1  P   0   1 -1       0  0         0  0         0  0         0  0  
002: -1    1  P   0   2 -1       0  0         0  0         0  0         0  0  
003: -1    1  P   0   3 -1       0  0         0  0         0  0         0  0  
004: -1    1  P   0   4 -1       0  0         0  0         0  0         0  0  
005: -1    1  P   0   5 -1       0  0         0  0         0  0         0  0  
006: -1    1  P   0   6 -1       0  0         0  0         0  0         0  0  
007: -1    1  P   0   7 -1       0  0         0  0         0  0         0  0
@cyring
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cyring commented Mar 25, 2025

Thank you so much.
I have various things to fix here.

We are getting the OPP frequencies: I will first improve the estimated base clock which should fall around 100MHz if specs say so.

Could you show the TSC running with 5 loops

corefreq-cli -c 5

@cyring
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cyring commented Mar 29, 2025

@jhart99 Hello,

Could please tell if your board is providing caches info ?
Either from Kernel, either from Device Tree, or from OpenSBI ?

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