@@ -188,27 +188,27 @@ void ICACHE_RAM_ATTR SoftwareSerial::preciseDelay(bool asyn, uint32_t savedPS) {
188
188
if (asyn)
189
189
{
190
190
resetPeriodStart ();
191
- m_periodDuration = 0 ;
192
191
}
193
192
if (asyn && !m_intTxEnabled) { savedPS = xt_rsil (15 ); }
194
193
}
195
194
196
195
void ICACHE_RAM_ATTR SoftwareSerial::writePeriod (
197
196
uint32_t dutyCycle, uint32_t offCycle, bool withStopBit, uint32_t savedPS) {
197
+ preciseDelay (false , savedPS);
198
198
if (dutyCycle) {
199
199
digitalWrite (m_txPin, HIGH);
200
200
m_periodDuration += dutyCycle;
201
201
bool asyn = withStopBit && !m_invert;
202
202
// Reenable interrupts while delaying to avoid other tasks piling up
203
- preciseDelay (asyn, savedPS);
203
+ if (asyn || offCycle) preciseDelay (asyn, savedPS);
204
204
// Disable interrupts again
205
205
}
206
206
if (offCycle) {
207
207
digitalWrite (m_txPin, LOW);
208
208
m_periodDuration += offCycle;
209
209
bool asyn = withStopBit && m_invert;
210
210
// Reenable interrupts while delaying to avoid other tasks piling up
211
- preciseDelay (asyn, savedPS);
211
+ if (asyn) preciseDelay (asyn, savedPS);
212
212
// Disable interrupts again
213
213
}
214
214
}
@@ -235,7 +235,6 @@ size_t ICACHE_RAM_ATTR SoftwareSerial::write(const uint8_t * buffer, size_t size
235
235
savedPS = xt_rsil (15 );
236
236
}
237
237
resetPeriodStart ();
238
- m_periodDuration = 0 ;
239
238
const uint32_t dataMask = ((1UL << m_dataBits) - 1 );
240
239
for (size_t cnt = 0 ; cnt < size; ++cnt, ++buffer) {
241
240
bool withStopBit = true ;
0 commit comments