LED blink
In this tutorial we are going to demonstrate how to blink the LEDs of your Redpitaya-124-14. The LEDs will be driven by the most-significant-bit (MSB) of a counter that continuously overflows. The counter is implemented within the Programable Logic (PL) and controlled through a simple PYQN Jupyter Notebook running on the Processing System (PS).
- Open Vivado and click on Create Project and hit Next.
- Set the name of the new project (e.g. LED_blink) and hit Next.
- Use the default project type (RTL Project) and hit Next.
- Leave the Add Sources screen empty and hit Next.
- Use Add File to include the constraints file within <FPGA-Notes-for-Scientists>/sdc/red_pitaya.xdc and hit Next.
- Under the Boards tab select Redpitaya-125-14 (see Setting up your system to install the required board files) and hit Next.
- After finishing this initial configurations, a new Vivado Project is created. You will see the Project Manager page:
- Create a new block design by clicking on Create Block Design (left panel). You can leave the default name, which will be design_1.
- Create a new block design by clicking on Create Block Design (left panel). The design name will default to design_1.
- Right-click on the blank design and select Add IP to instantiate:
- ZYNQ 7 Processing System
- AXI GPIO
- Click on Run Block Automation (green field above your design) to route the DDR and FIXED_IO ports of the ZYNQ instance. To this end, leave the configuration window in its default state.
- Click on Run Connection Automation (green field above your design) to create the required clocking, reset and AXI interconnect infrastructure. To this end, within the configuration window only select S_AXI. We do not select GPIO, because we will manually configure the AXI GPIO in the following step.
- After running block & connection automation, the design will becomes:
- Double-click on the AXI GPIO instance and enable Channel 1 and Channel 2 as outputs of 1 and 32 bits, respectively. Later in the design process, we will use Channel 1 to reset the counter logic and Channel 2 to define the counter increment value.
- Double-click on the ZYNQ instance and verify that FCLK_CLK0 is enabled and set to 50 MHz (under Clock Configuration --> PL Fabric Clocks).
- The next step is to create a counter logic with variable counter increment. Click on Add Sources (left panel) and select Add or create design sources.
- At this point you can either select and already existing HDL file or create a new one. We will follow the latter option:
- Define the module ports (this can be changed later within the HDL code).
- The new source file (counter.vhd) will be added to the source tree. Open it to create your custom counter logic:
ℹ️ You can use <FPGA-Notes-for-Scientists>/hdl/counter.vhd (link here) as a template for a HDL counter.