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Pau Gómez edited this page May 14, 2021 · 34 revisions

About this tutorial

⏱️ 30 min

In this tutorial we are going to demonstrate how to blink the LEDs of your Redpitaya-124-14. The LEDs will be driven by the most-significant-bit (MSB) of a counter that continuously overflows. The counter is implemented within the Programable Logic (PL) and controlled through a simple PYQN Jupyter Notebook running on the Processing System (PS).

Building the Vivado Design

Create a new Vivado Project

  • Open Vivado and click on Create Project and hit Next.
  • Set the name of the new project (e.g. LED_blink) and hit Next.
  • Use the default project type (RTL Project) and hit Next.
  • Leave the Add Sources screen empty and hit Next.
  • Use Add File to include the constraints file within <FPGA-Notes-for-Scientists>/sdc/red_pitaya.xdc and hit Next.
  • Under the Boards tab select Redpitaya-125-14 (see here for instructions to install the Redpitaya-125-14 board files) and hit Next.
  • After finishing this initial configurations, a new Vivado Project is created. You will see the Project Manager page:

Create a new Block Design

  • Create a new block design by clicking on Create Block Design (left panel). The design name will default to design_1.
  • Right-click on the blank design and select Add IP to instantiate:
    • ZYNQ 7 Processing System
    • AXI GPIO
  • Click on Run Block Automation (green field above your design) to route the DDR and FIXED_IO ports of the ZYNQ instance. To this end, leave the configuration window in its default state.
  • Click on Run Connection Automation (green field above your design) to create the required clocking, reset and AXI interconnect infrastructure. To this end, within the configuration window only select S_AXI. We do not select GPIO, because we will manually configure & connect the AXI GPIO.
  • After running block & connection automation, the design becomes:
  • Double-click on the AXI GPIO instance and enable Channel 1 and Channel 2 as outputs of 1 and 32 bits, respectively. Later in the design process, we will use Channel 1 to reset the counter logic and Channel 2 to define the counter increment value.
  • Double-click on the ZYNQ instance and verify (under Clock Configuration --> PL Fabric Clocks) that FCLK_CLK0 is enabled and set to 50 MHz.

Create a HDL counter

  • The next step is to create a counter logic with variable counter increment. Click on Add Sources (left panel) and select Add or create design sources.
  • At this point you can either select and already existing HDL file or create a new one. We will follow the latter.
  • Define the module ports (they can also be changed later, within the HDL code).
  • The new source file (counter.vhd) will be added to the project source tree.

  • Edit counter.vhd to include the counter logic (see ℹ️).

  • Add the HDL counter module to your design. To this end, right-click on the design and select Add Module.

ℹ️ A ready-to-use HDL counter is available under <FPGA-Notes-for-Scientists>/hdl/counter.vhd.

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