Add counter test

Author: M0stafaRady

verilog/dv/cocotb/cocotb_tests.py

@@ -1 +1,2 @@
-from frigate_test.gpio_portA.gpio_portA import gpio_portA
+from frigate_test.gpio_portA.gpio_portA import gpio_portA
+from user_proj_tests.counter.counter import counter

verilog/dv/cocotb/user_counter.h

@@ -0,0 +1,25 @@
+#ifndef USER_COUNTER_H
+#define USER_COUNTER_H
+
+typedef struct _EF_USER_COUNTER_TYPE_ {
+    __RW	COUNT;
+	__RW	CTRL;
+} EF_USER_COUNTER_TYPE;
+
+typedef struct _EF_USER_COUNTER_TYPE_ *EF_USER_COUNTER_TYPE_PTR;     // Pointer to the register structure
+#define USER_COUNTER ((EF_USER_COUNTER_TYPE_PTR)0x60000000)
+
+
+void EF_USER_COUNTER_enable(EF_USER_COUNTER_TYPE_PTR counter) {
+    counter->CTRL = 1;
+};
+
+void EF_USER_COUNTER_disable(EF_USER_COUNTER_TYPE_PTR counter) {
+    counter->CTRL = 0;
+};
+
+int read_count(EF_USER_COUNTER_TYPE_PTR counter) {
+    return counter->COUNT;
+};
+
+#endif // USER_COUNTER_H

verilog/dv/cocotb/user_proj_tests/counter/counter.c

@@ -0,0 +1,27 @@
+#include <frigate_regs.h>
+#include <EF_GPIO8.h>
+#include <EF_GPIO8.c>
+#include <clk_rst.h>
+#include "user_counter.h"
+#include <system_regs.h>
+
+/*
+test sequence eable the counter 
+read the counter value and write it at GPIOB (port3)
+*/
+void main(){
+    CLK_RST_GCLK_EN(0b111); // enable pclk 
+    CLK_RST_USER_CLK_CTRL(1); // enable user clock
+    SYSREG_setUserAHBEn(1); // enable user interface
+    EF_GPIO8_setGclkEnable(PORT_H, 1); // required in design with clock gating.
+    EF_GPIO8_setPinDirection(PORT_H, 7, GPIO8_OUTPUT); // use GPIOH 0 as indicator
+    EF_GPIO8_writeAllDirection(PORT_B,0xFF); // configure port as output
+    // enable counter 
+    EF_USER_COUNTER_enable(USER_COUNTER);
+    while (1) {
+        EF_GPIO8_writeData(PORT_H ,0);
+        int count_val = read_count(USER_COUNTER);
+        EF_GPIO8_writeData(PORT_B ,count_val);
+        EF_GPIO8_writeData(PORT_H ,0xFF); // read data 
+    }
+}

verilog/dv/cocotb/user_proj_tests/counter/counter.py

@@ -0,0 +1,34 @@
+from caravel_cocotb.caravel_interfaces import report_test
+import cocotb
+from common import test_configure_ml
+import random
+from frigate_test.gpio import GPIOsPortB, GPIOsPortA, GPIOsPortH
+
+@cocotb.test()
+@report_test
+async def counter(dut):
+    caravelEnv = await test_configure_ml(dut, timeout_cycles=78129)
+    cocotb.log.info("[TEST] Start counter test")
+    counter_gpio = GPIOsPortA(caravelEnv) # RTL connects user counter value to GPIOA
+    gpio_port_b = GPIOsPortB(caravelEnv) # for monitoring value read from software
+    gpio_port_h = GPIOsPortH(caravelEnv) # new value indicator
+    shift = 0
+    old_counter_val = 0
+    old_software_val = 0
+    for i in range(10):
+        await gpio_port_h.wait_gpio_pin(7, 1)
+        counter_val = counter_gpio.monitor_gpio(7, 0).integer
+        software_val = gpio_port_b.monitor_gpio(7, 0).integer
+        cocotb.log.info(f"[TEST] counter_val: {counter_val}, software_val: {software_val} shift {counter_val - software_val}")
+        if i == 0:
+            shift = counter_val - software_val
+            old_counter_val = counter_val
+            old_software_val = software_val
+        else:
+            if counter_val - software_val != shift:
+                cocotb.log.error(f"[TEST] shift error shift = {counter_val - software_val} expected shift = {shift}")
+            if counter_val <= old_counter_val:
+                cocotb.log.error(f"[TEST] counting direction error counter_val: {counter_val} <= old_counter_val: {old_counter_val}")
+            if software_val <= old_software_val:
+                cocotb.log.error(f"[TEST] counting direction error software_val: {software_val} <= old_software_val: {old_software_val}")
+        await gpio_port_h.wait_gpio_pin(7, 0)

verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml

@@ -1,2 +1,3 @@
 Tests: 
   - {name: gpio_portA, sim: RTL}
+  - {name: counter, sim: RTL}

verilog/dv/cocotb/user_run_test.py

@@ -186,6 +186,8 @@ def _iverilog_docker_command_str(self, command=""):
 
     def iverilog_compile(self):
         macros = " -D" + " -D".join(self.test.macros)
+        if os.path.isfile(f"{self.test.compilation_dir}/sim.vvp"):
+            os.remove(f"{self.test.compilation_dir}/sim.vvp")
         compile_command = (
             f"cd {self.test.compilation_dir} &&"
             f"iverilog -g2012 -Ttyp {macros} {self.iverilog_dirs} -o {self.test.compilation_dir}/sim.vvp -s caravel_top"
@@ -201,6 +203,8 @@ def iverilog_compile(self):
 
 
     def vcs_compile(self):
+        if os.path.isfile(f"{self.test.compilation_dir}/simv"):
+            os.remove(f"{self.test.compilation_dir}/simv")
         macros = " +define+" + " +define+".join(self.test.macros)
         vlogan_cmd = f"cd {self.test.compilation_dir}; vlogan -full64 -negdelay -sverilog +error+30 {self.paths.FRIGATE_ROOT}/verilog/vip/toplevel_cocotb.v {self.vcs_dirs}  {macros}   -l {self.test.compilation_dir}/analysis.log -o {self.test.compilation_dir} "
         self.run_command_write_to_file(vlogan_cmd, self.test.compilation_log, self.logger, quiet=False if self.args.verbosity == "debug" else True)

verilog/includes/includes.rtl.frigate_user_project

@@ -16,3 +16,5 @@
 
 # defines 
 -v $(USER_PROJECT_VERILOG)/rtl/user_defines.v
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/ahb_counter.v