From 37ac79b93eefae3b4ff9ce954e82f913ec8d6d56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Thu, 12 Sep 2024 09:48:15 +0200 Subject: [PATCH] build: io: make oe2 of DDRTristate optional MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit make oe2 of DDRTristate optional. Signed-off-by: Fin Maaß --- litex/build/efinix/common.py | 2 +- litex/build/io.py | 4 ++-- litex/build/lattice/common.py | 3 ++- litex/build/xilinx/common.py | 2 +- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py index fa787f9e23..9be3be90f8 100644 --- a/litex/build/efinix/common.py +++ b/litex/build/efinix/common.py @@ -252,7 +252,7 @@ def lower(dr): class EfinixDDRTristateImpl(Module): def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk): - assert oe1 == oe2 + assert oe2 is None io_name = platform.get_pin_name(io) io_pad = platform.get_pin_location(io) io_prop = platform.get_pin_properties(io) diff --git a/litex/build/io.py b/litex/build/io.py index 8a54454500..08d58627a5 100644 --- a/litex/build/io.py +++ b/litex/build/io.py @@ -184,12 +184,12 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): _oe = Signal() _i = Signal() self.specials += DDROutput(o1, o2, _o, clk) - self.specials += DDROutput(oe1, oe2, _oe, clk) + self.specials += DDROutput(oe1, oe2, _oe, clk) if oe2 is not None else SDROutput(oe1, _oe, clk) self.specials += DDRInput(_i, i1, i2, clk) self.specials += Tristate(io, _o, _oe, _i) class DDRTristate(Special): - def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk=ClockSignal()): + def __init__(self, io, o1, o2, oe1, oe2=None, i1=Signal(), i2=Signal(), clk=ClockSignal()): Special.__init__(self) self.io = io self.o1 = o1 diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py index 3f3f78e637..cec5ca51dc 100644 --- a/litex/build/lattice/common.py +++ b/litex/build/lattice/common.py @@ -305,11 +305,12 @@ def lower(dr): class LatticeNXDDRTristateImpl(Module): def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): + assert oe2 is None _o = Signal() _oe = Signal() _i = Signal() self.specials += DDROutput(o1, o2, _o, clk) - self.specials += SDROutput(oe1 | oe2, _oe, clk) + self.specials += SDROutput(oe1, _oe, clk) self.specials += DDRInput(_i, i1, i2, clk) self.specials += Tristate(io, _o, _oe, _i) _oe.attr.add("syn_useioff") diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index d0d6bf0f63..0f2231f70b 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -164,7 +164,7 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): _oe_n = Signal() _i = Signal() self.specials += DDROutput(o1, o2, _o, clk) - self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk) + self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk) if oe2 is not None else SDROutput(~oe1, _oe_n, clk) self.specials += DDRInput(_i, i1, i2, clk) self.specials += Instance("IOBUF", io_IO = io,