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CHANGELOG.md

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CHANGELOG

Introduction

The LiteX M2 SDR project is actively under development and does not yet have formal releases. However, we maintain this changelog to allow users and potential clients of the hardware to follow the project's progress and stay up to date with the latest features and improvements. The updates below are summarized by quarter, highlighting major advancements to provide a clear overview of the project's evolution.

[> 2025 Q1 (Jan - Mar)

Enhanced Hardware and Software Integration with New Diagnostic Tools

  • Enhanced gateware with optional CSR in measurement module and added simultaneous clock latching capability.
  • Improved software ecosystem by introducing libliteeth for Etherbone files and adapting SoapySDR driver to use it.
  • Optimized power usage by defaulting to 2 PCIe lanes for the M2 variant.
  • Extended sample rate support down to 0.5 Msps with FIR Interpolation/Decimation on AD9361, including LTE/5G NR options.
  • Added initial dashboard and test utilities (e.g., AGC, DMA, clock panels) for better hardware monitoring and debugging.
  • Integrated hardware time generation with TimeGenerator module and PPS support for timestamp coherency.
  • Improved documentation and installation process, including Raspberry Pi 5 support and updated README for commercial availability.

[> 2024 Q4 (Oct - Dec)

Networking Enhancements and Sample Rate Flexibility

  • Introduced Ethernet-based streaming and control options alongside PCIe, with dynamic IP configuration.
  • Enhanced sample rate handling with 122.88MSPS support and oversampling tests for AD9361.
  • Added runtime switching between 1T1R and 2T2R modes in SoapySDR driver.
  • Fixed key bugs (e.g., RX vs TX mix-up) and improved stability with mutexes for gain/bandwidth settings.
  • Expanded hardware support with additional pullups on SI5351 I2C and IOMMU passthrough tips.

[> 2024 Q3 (Jul - Sep)

Ethernet Streaming and Multi-Protocol Support

  • Added initial UDP streaming for RF RX samples over Ethernet.
  • Implemented crossbar in target to streamline stream multiplexing/demultiplexing between Comms and RFIC.
  • Enabled external 10MHz ClkIn support via uFL for SI5351 and tested SI5351C configuration.
  • Supported simultaneous PCIe, Ethernet (1000BaseX/2500BaseX), and SATA with SharedQPLL module.
  • Added OrangePi 5 Max documentation for broader platform compatibility.

[> 2024 Q2 (Apr - Jun)

Performance Boosts and Mode Flexibility

  • Introduced multiboot bitstream flashing and switched to 4 PCIe lanes by default for improved performance.
  • Added 8-bit mode support in gateware and software, with automatic TX/RX delay calibration.
  • Integrated SPI Flash support for updates over PCIe and AD9361 temperature sensor in SoapySDR.
  • Enhanced clocking with SI5351_EN control and 2500BaseX Ethernet support.
  • Improved RFIC oversampling options and timestamp handling with 64-bit counter optimization.

[> 2024 Q1 (Jan - Mar)

Project Foundation and Connectivity Setup

  • Initial project setup with SI5351 clocking (148.5MHz/148.35MHz) and 1000BaseX Etherbone support.
  • Added AD9361 SPI integration and basic RFIC connectivity with debug tools (LiteScope).
  • Established PCIe X1 support and foundational software utilities (e.g., litex_m2sdr_rf, liblitexm2sdr).
  • Laid groundwork with platform and target definitions, including JTAG and SFP support.