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Merge branch 'feature/refactor_i2s_driver' into 'master'
refactor(i2s): Refactor i2s driver for esp8266 idf See merge request sdk/ESP8266_RTOS_SDK!712
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‎components/esp8266/include/esp8266/i2s_register.h

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// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SLC_REGISTER_H_
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#define _SLC_REGISTER_H_
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#include "eagle_soc.h"
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#define REG_I2S_BASE (0x60000e00)
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#define I2STXFIFO (REG_I2S_BASE + 0x0000)
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#define I2SRXFIFO (REG_I2S_BASE + 0x0004)
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#define I2SCONF (REG_I2S_BASE + 0x0008)
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#define I2S_BCK_DIV_NUM 0x0000003F
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#define I2S_BCK_DIV_NUM_S 22
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#define I2S_CLKM_DIV_NUM 0x0000003F
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#define I2S_CLKM_DIV_NUM_S 16
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#define I2S_BITS_MOD 0x0000000F
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#define I2S_BITS_MOD_S 12
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#define I2S_RECE_MSB_SHIFT (BIT(11))
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#define I2S_TRANS_MSB_SHIFT (BIT(10))
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#define I2S_I2S_RX_START (BIT(9))
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#define I2S_I2S_TX_START (BIT(8))
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#define I2S_MSB_RIGHT (BIT(7))
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#define I2S_RIGHT_FIRST (BIT(6))
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#define I2S_RECE_SLAVE_MOD (BIT(5))
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#define I2S_TRANS_SLAVE_MOD (BIT(4))
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#define I2S_I2S_RX_FIFO_RESET (BIT(3))
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#define I2S_I2S_TX_FIFO_RESET (BIT(2))
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#define I2S_I2S_RX_RESET (BIT(1))
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#define I2S_I2S_TX_RESET (BIT(0))
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#define I2S_I2S_RESET_MASK 0xf
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#define I2SINT_RAW (REG_I2S_BASE + 0x000c)
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#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
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#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
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#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
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#define I2SINT_ST (REG_I2S_BASE + 0x0010)
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#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
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#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
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#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
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#define I2SINT_ENA (REG_I2S_BASE + 0x0014)
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#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
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#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
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#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
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#define I2SINT_CLR (REG_I2S_BASE + 0x0018)
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#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
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#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
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#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
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#define I2STIMING (REG_I2S_BASE + 0x001c)
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#define I2S_TRANS_BCK_IN_INV (BIT(22))
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#define I2S_RECE_DSYNC_SW (BIT(21))
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#define I2S_TRANS_DSYNC_SW (BIT(20))
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#define I2S_RECE_BCK_OUT_DELAY 0x00000003
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#define I2S_RECE_BCK_OUT_DELAY_S 18
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#define I2S_RECE_WS_OUT_DELAY 0x00000003
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#define I2S_RECE_WS_OUT_DELAY_S 16
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#define I2S_TRANS_SD_OUT_DELAY 0x00000003
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#define I2S_TRANS_SD_OUT_DELAY_S 14
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#define I2S_TRANS_WS_OUT_DELAY 0x00000003
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#define I2S_TRANS_WS_OUT_DELAY_S 12
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#define I2S_TRANS_BCK_OUT_DELAY 0x00000003
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#define I2S_TRANS_BCK_OUT_DELAY_S 10
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#define I2S_RECE_SD_IN_DELAY 0x00000003
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#define I2S_RECE_SD_IN_DELAY_S 8
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#define I2S_RECE_WS_IN_DELAY 0x00000003
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#define I2S_RECE_WS_IN_DELAY_S 6
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#define I2S_RECE_BCK_IN_DELAY 0x00000003
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#define I2S_RECE_BCK_IN_DELAY_S 4
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#define I2S_TRANS_WS_IN_DELAY 0x00000003
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#define I2S_TRANS_WS_IN_DELAY_S 2
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#define I2S_TRANS_BCK_IN_DELAY 0x00000003
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#define I2S_TRANS_BCK_IN_DELAY_S 0
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#define I2S_FIFO_CONF (REG_I2S_BASE + 0x0020)
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#define I2S_I2S_RX_FIFO_MOD 0x00000007
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#define I2S_I2S_RX_FIFO_MOD_S 16
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#define I2S_I2S_TX_FIFO_MOD 0x00000007
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#define I2S_I2S_TX_FIFO_MOD_S 13
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#define I2S_I2S_DSCR_EN (BIT(12))
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#define I2S_I2S_TX_DATA_NUM 0x0000003F
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#define I2S_I2S_TX_DATA_NUM_S 6
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#define I2S_I2S_RX_DATA_NUM 0x0000003F
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#define I2S_I2S_RX_DATA_NUM_S 0
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#define I2SRXEOF_NUM (REG_I2S_BASE + 0x0024)
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#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
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#define I2S_I2S_RX_EOF_NUM_S 0
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#define I2SCONF_SIGLE_DATA (REG_I2S_BASE + 0x0028)
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#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
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#define I2S_I2S_SIGLE_DATA_S 0
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#define I2SCONF_CHAN (REG_I2S_BASE + 0x002c)
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#define I2S_RX_CHAN_MOD 0x00000003
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#define I2S_RX_CHAN_MOD_S 3
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#define I2S_TX_CHAN_MOD 0x00000007
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#define I2S_TX_CHAN_MOD_S 0
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#endif

‎components/esp8266/include/esp8266/i2s_struct.h

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// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "esp8266/eagle_soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ESP8266 I2S Register Definitions */
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typedef volatile struct {
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uint32_t tx_fifo;
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uint32_t rx_fifo;
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union {
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struct {
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uint32_t tx_reset: 1;
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uint32_t rx_reset: 1;
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uint32_t tx_fifo_reset: 1;
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uint32_t rx_fifo_reset: 1;
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uint32_t tx_slave_mod: 1;
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uint32_t rx_slave_mod: 1;
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uint32_t right_first: 1;
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uint32_t msb_right: 1;
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uint32_t tx_start: 1;
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uint32_t rx_start: 1;
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uint32_t tx_msb_shift: 1;
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uint32_t rx_msb_shift: 1;
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uint32_t bits_mod: 4;
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uint32_t clkm_div_num: 6;
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uint32_t bck_div_num: 6;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} conf;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_st;
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union {
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struct {
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uint32_t rx_take_data: 1;
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uint32_t tx_put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t take_data: 1;
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uint32_t put_data: 1;
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uint32_t rx_wfull: 1;
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uint32_t rx_rempty: 1;
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uint32_t tx_wfull: 1;
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uint32_t tx_rempty: 1;
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uint32_t reserved6: 26;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t tx_bck_in_delay: 2;
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uint32_t tx_ws_in_delay: 2;
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uint32_t rx_bck_in_delay: 2;
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uint32_t rx_ws_in_delay: 2;
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uint32_t rx_sd_in_delay: 2;
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uint32_t tx_bck_out_delay: 2;
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uint32_t tx_ws_out_delay: 2;
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uint32_t tx_sd_out_delay: 2;
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uint32_t rx_ws_out_delay: 2;
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uint32_t rx_bck_out_delay: 2;
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uint32_t tx_dsync_sw: 1;
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uint32_t rx_dsync_sw: 1;
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uint32_t tx_bck_in_inv: 1;
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uint32_t reserved23: 9;
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};
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uint32_t val;
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} timing;
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union {
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struct {
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uint32_t rx_data_num: 6;
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uint32_t tx_data_num: 6;
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uint32_t dscr_en: 1;
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uint32_t tx_fifo_mod: 3;
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uint32_t rx_fifo_mod: 3;
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uint32_t reserved19: 13;
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};
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uint32_t val;
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} fifo_conf;
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uint32_t rx_eof_num;
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uint32_t conf_single_data;
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union {
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struct {
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uint32_t tx_chan_mod: 3;
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uint32_t rx_chan_mod: 2;
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uint32_t reserved5: 27;
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};
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uint32_t val;
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} conf_chan;
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} i2s_struct_t;
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extern volatile i2s_struct_t I2S;
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#ifdef __cplusplus
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}
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#endif /* end of __cplusplus */
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