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NouranAbdelazizNouranAbdelaziz
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update wrappers to remove unused TXDATA_WIRE + update EFIS links in docs
1 parent 859dd10 commit 33584f0

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‎EF_SPI.yaml

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@@ -8,7 +8,7 @@ info:
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author: Efabless Corp.
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email: ip_admin@efabless.com
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version: v1.1.0
11-
date: 2025-01-23
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date: 23-01-2025
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category: digital
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tags:
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- peripheral

‎README.md

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@@ -223,8 +223,8 @@ VERILOG_DEFINES:
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- CLKG_SKY130_HD
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```
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## Firmware Drivers:
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Firmware drivers for EF_SPI can be found in the [Drivers](https://github.com/efabless/EFIS/tree/main/Drivers) directory in the [EFIS](https://github.com/efabless/EFIS) (Efabless Firmware Interface Standard) repo. EF_SPI driver documentation is available [here](https://github.com/efabless/EFIS/blob/main/Drivers/docs/EF_Driver_SPI/README.md).
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You can also find an example C application using the EF_SPI drivers [here](https://github.com/efabless/EFIS/tree/main/Drivers/docs/EF_Driver_SPI/example).
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Firmware drivers for EF_SPI can be found in the [Drivers](https://github.com/efabless/EFIS/tree/main/Drivers) directory in the [EFIS](https://github.com/efabless/EFIS) (Efabless Firmware Interface Standard) repo. EF_SPI driver documentation is available [here](https://github.com/efabless/EFIS/blob/main/Drivers/Docs/EF_SPI/README.md).
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You can also find an example C application using the EF_SPI drivers [here](https://github.com/efabless/EFIS/tree/main/Drivers/Docs/EF_SPI/example).
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## Installation:
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You can install the IP either by cloning this repository or by using [IPM](https://github.com/efabless/IPM).
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### 1. Using [IPM](https://github.com/efabless/IPM):

‎fw/EF_SPI_regs.h

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@@ -1,5 +1,5 @@
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/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55

‎hdl/rtl/bus_wrappers/EF_SPI_AHBL.dev.v

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@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
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Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -107,7 +107,6 @@ module EF_SPI_AHBL #(
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// Register Definitions
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wire [8-1:0] RXDATA_WIRE;
109109

110-
wire [8-1:0] TXDATA_WIRE;
111110

112111
reg [1:0] CFG_REG;
113112
assign CPOL = CFG_REG[0 : 0];
@@ -237,7 +236,6 @@ module EF_SPI_AHBL #(
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assign HRDATA =
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(last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
240-
(last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
241239
(last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
242240
(last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
243241
(last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/EF_SPI_AHBL.v

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -124,8 +124,6 @@ module EF_SPI_AHBL #(
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// Register Definitions
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wire [8-1:0] RXDATA_WIRE;
126126

127-
wire [8-1:0] TXDATA_WIRE;
128-
129127
reg [1:0] CFG_REG;
130128
assign CPOL = CFG_REG[0 : 0];
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assign CPHA = CFG_REG[1 : 1];
@@ -288,7 +286,6 @@ module EF_SPI_AHBL #(
288286

289287
assign HRDATA =
290288
(last_HADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
291-
(last_HADDR[16-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
292289
(last_HADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
293290
(last_HADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
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(last_HADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/EF_SPI_APB.dev.v

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@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -107,7 +107,6 @@ module EF_SPI_APB #(
107107
// Register Definitions
108108
wire [8-1:0] RXDATA_WIRE;
109109

110-
wire [8-1:0] TXDATA_WIRE;
111110

112111
reg [1:0] CFG_REG;
113112
assign CPOL = CFG_REG[0 : 0];
@@ -237,7 +236,6 @@ module EF_SPI_APB #(
237236

238237
assign PRDATA =
239238
(PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
240-
(PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
241239
(PADDR[`APB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
242240
(PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
243241
(PADDR[`APB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/EF_SPI_APB.v

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -107,8 +107,6 @@ module EF_SPI_APB #(
107107
// Register Definitions
108108
wire [ 8-1:0] RXDATA_WIRE;
109109

110-
wire [ 8-1:0] TXDATA_WIRE;
111-
112110
reg [ 1:0] CFG_REG;
113111
assign CPOL = CFG_REG[0 : 0];
114112
assign CPHA = CFG_REG[1 : 1];
@@ -271,7 +269,6 @@ module EF_SPI_APB #(
271269

272270
assign PRDATA =
273271
(PADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
274-
(PADDR[16-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
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(PADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
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(PADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
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(PADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/EF_SPI_WB.dev.v

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@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -107,7 +107,6 @@ module EF_SPI_WB #(
107107
// Register Definitions
108108
wire [8-1:0] RXDATA_WIRE;
109109

110-
wire [8-1:0] TXDATA_WIRE;
111110

112111
reg [1:0] CFG_REG;
113112
assign CPOL = CFG_REG[0 : 0];
@@ -237,7 +236,6 @@ module EF_SPI_WB #(
237236

238237
assign dat_o =
239238
(adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
240-
(adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
241239
(adr_i[`WB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
242240
(adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
243241
(adr_i[`WB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/EF_SPI_WB.v

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
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Author: Efabless Corp. (ip_admin@efabless.com)
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@@ -109,8 +109,6 @@ module EF_SPI_WB #(
109109
// Register Definitions
110110
wire [ 8-1:0] RXDATA_WIRE;
111111

112-
wire [ 8-1:0] TXDATA_WIRE;
113-
114112
reg [ 1:0] CFG_REG;
115113
assign CPOL = CFG_REG[0 : 0];
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assign CPHA = CFG_REG[1 : 1];
@@ -271,7 +269,6 @@ module EF_SPI_WB #(
271269

272270
assign dat_o =
273271
(adr_i[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
274-
(adr_i[16-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
275272
(adr_i[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
276273
(adr_i[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
277274
(adr_i[16-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/dft/EF_SPI_AHBL_DFT.dev.v

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -108,7 +108,6 @@ module EF_SPI_AHBL #(
108108
// Register Definitions
109109
wire [8-1:0] RXDATA_WIRE;
110110

111-
wire [8-1:0] TXDATA_WIRE;
112111

113112
reg [1:0] CFG_REG;
114113
assign CPOL = CFG_REG[0 : 0];
@@ -238,7 +237,6 @@ module EF_SPI_AHBL #(
238237

239238
assign HRDATA =
240239
(last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
241-
(last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
242240
(last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
243241
(last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
244242
(last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/dft/EF_SPI_AHBL_DFT.v

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@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -125,8 +125,6 @@ module EF_SPI_AHBL #(
125125
// Register Definitions
126126
wire [8-1:0] RXDATA_WIRE;
127127

128-
wire [8-1:0] TXDATA_WIRE;
129-
130128
reg [1:0] CFG_REG;
131129
assign CPOL = CFG_REG[0 : 0];
132130
assign CPHA = CFG_REG[1 : 1];
@@ -289,7 +287,6 @@ module EF_SPI_AHBL #(
289287

290288
assign HRDATA =
291289
(last_HADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
292-
(last_HADDR[16-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
293290
(last_HADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
294291
(last_HADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
295292
(last_HADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/dft/EF_SPI_APB_DFT.dev.v

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -108,7 +108,6 @@ module EF_SPI_APB #(
108108
// Register Definitions
109109
wire [8-1:0] RXDATA_WIRE;
110110

111-
wire [8-1:0] TXDATA_WIRE;
112111

113112
reg [1:0] CFG_REG;
114113
assign CPOL = CFG_REG[0 : 0];
@@ -238,7 +237,6 @@ module EF_SPI_APB #(
238237

239238
assign PRDATA =
240239
(PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
241-
(PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
242240
(PADDR[`APB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
243241
(PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
244242
(PADDR[`APB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/dft/EF_SPI_APB_DFT.v

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -108,8 +108,6 @@ module EF_SPI_APB #(
108108
// Register Definitions
109109
wire [ 8-1:0] RXDATA_WIRE;
110110

111-
wire [ 8-1:0] TXDATA_WIRE;
112-
113111
reg [ 1:0] CFG_REG;
114112
assign CPOL = CFG_REG[0 : 0];
115113
assign CPHA = CFG_REG[1 : 1];
@@ -272,7 +270,6 @@ module EF_SPI_APB #(
272270

273271
assign PRDATA =
274272
(PADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
275-
(PADDR[16-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
276273
(PADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
277274
(PADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
278275
(PADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/dft/EF_SPI_WB_DFT.dev.v

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@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
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Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -108,7 +108,6 @@ module EF_SPI_WB #(
108108
// Register Definitions
109109
wire [8-1:0] RXDATA_WIRE;
110110

111-
wire [8-1:0] TXDATA_WIRE;
112111

113112
reg [1:0] CFG_REG;
114113
assign CPOL = CFG_REG[0 : 0];
@@ -238,7 +237,6 @@ module EF_SPI_WB #(
238237

239238
assign dat_o =
240239
(adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
241-
(adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
242240
(adr_i[`WB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
243241
(adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
244242
(adr_i[`WB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :

‎hdl/rtl/bus_wrappers/dft/EF_SPI_WB_DFT.v

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. (ip_admin@efabless.com)
55
@@ -110,8 +110,6 @@ module EF_SPI_WB #(
110110
// Register Definitions
111111
wire [ 8-1:0] RXDATA_WIRE;
112112

113-
wire [ 8-1:0] TXDATA_WIRE;
114-
115113
reg [ 1:0] CFG_REG;
116114
assign CPOL = CFG_REG[0 : 0];
117115
assign CPHA = CFG_REG[1 : 1];
@@ -272,7 +270,6 @@ module EF_SPI_WB #(
272270

273271
assign dat_o =
274272
(adr_i[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
275-
(adr_i[16-1:0] == TXDATA_REG_OFFSET) ? TXDATA_WIRE :
276273
(adr_i[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
277274
(adr_i[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
278275
(adr_i[16-1:0] == PR_REG_OFFSET) ? PR_REG :

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