Low_Power_Multidimensional_Sorters

Low Power Multidimensional Sorters using Clock Gating and Index Sorting (Paper Link)

Published in: 2023 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)
DOI: 10.1109/CONECCT57959.2023.10234758

Bluespec SystemVerilog Implementation

Sorter Implementation	Design Files
CAE(Compare and Exchange)	cae.bsv
BM4 (Bitonic Merge 4)	bm4.bsv
BM8 (Bitonic Merge 8)	bm8.bsv
MDSA_bitonic	mdsa_bitonic.bsv

Steps to run simulations of the CAE, BM4, BM8 and MDSA_Bitonic in the GitHub Repository

1. Clone the repository:

   git clone https://github.com/govardhnn/Low_Power_Multidimensional_Sorters.git

2. Navigate the the build directory of the BSV collateral

   cd bsv/build

3. Modify the makefile.inc to select the module to simulate

For CAE:

TB_BSV:= cae_testbench

For BM4:

TB_BSV:= bm4_testbench

For BM8:

TB_BSV:= bm8_testbench

For MDSA:

TB_BSV:= mdsa_bitonic_testbench

1. To run the simulation with the Bluespec Compiler (bsc):

   make all_vsim

The generated verilog can be found in the verilog_dir directory

Note: To get a vcd dump of the simulation, rerun the executable with the +bscvcd argument. Eg. ./mk_mdsa_bitonic_testbench_vsim +bscvcd Or, add the +bscvcd flag to the v_simulate target in the Makefile

Verilog Implementation (Capstone Legacy Codebase)

Maturity Level: Passed Gate Level Simulations with Positive Slack for 50MHz
Collateral: Verilog Design Files, SystemVerilog Layered TestBench, Constraints File

Library Used: Synopsys 90nm Typical VT (saed90nm_typ.lib)

Sorter Implementation	MDSA designs
Bitonic (24 CAE)	MDSA_bitonic MDSA_bitonic_index_merge MDSA_bitonic_index_pipeline
Hybrid (23 CAE)	MDSA_hybrid MDSA_hybrid_index
Odd Even (19 CAE)	MDSA_OE MDSA_OE_index

Testing Methodology: SystemVerilog Layered Testbench (for 100 iterations, using constraints and randomization for generating VCD)

• We further applied clock gating to all the above designs for further power reduction.

• Total 14 Implementations
  Lowest Power: MDSA Bitonic with Index and Clock Gating
  Lowest Area: MDSA Odd Even with Clock Gating

Background of the project

BTech ECE Capstone Project (Team: N-08, Batch of ECE 2023) at PES University, Bangalore
Guide: Dr. Sudeendra Kumar K

Licenses

bsv/LICENSE
verilog/LICENSE