Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

dwc2: flush fifo in dcd_edpt_close_all() #2589

Merged
merged 2 commits into from
Apr 11, 2024
Merged

dwc2: flush fifo in dcd_edpt_close_all() #2589

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
03cfe90
flush fifo in dcd_edpt_close_all()
HiFiPhile Apr 10, 2024
79cbe93
separate flush tx/rx fifo
hathach Apr 11, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
37 changes: 21 additions & 16 deletions src/portable/synopsys/dwc2/dcd_dwc2.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,17 @@ static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
}

TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
// flush TX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
}
TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_rx(dwc2_regs_t* dwc2) {
// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
}

static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
Expand Down Expand Up @@ -225,8 +236,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
}

// Flush the FIFO, and wait until we have confirmed it cleared.
dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {}
fifo_flush_tx(dwc2, epnum);
} else {
dwc2_epout_t* epout = dwc2->epout;

Expand Down Expand Up @@ -270,13 +280,8 @@ static void bus_reset(uint8_t rhport) {
dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
}

// flush all TX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}

// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
fifo_flush_tx(dwc2, 0x10); // all tx fifo
fifo_flush_rx(dwc2);

// 2. Set up interrupt mask
dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
Expand Down Expand Up @@ -584,13 +589,8 @@ void dcd_init(uint8_t rhport) {
// (non zero-length packet), send STALL back and discard.
dwc2->dcfg |= DCFG_NZLSOHSK;

// flush all TX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}

// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
fifo_flush_tx(dwc2, 0x10); // all tx fifo
fifo_flush_rx(dwc2);

// Clear all interrupts
uint32_t int_mask = dwc2->gintsts;
Expand Down Expand Up @@ -708,8 +708,13 @@ void dcd_edpt_close_all(uint8_t rhport) {
xfer_status[n][TUSB_DIR_IN].max_size = 0;
}

// reset allocated fifo OUT
dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
// reset allocated fifo IN
_allocated_fifo_words_tx = 16;

fifo_flush_tx(dwc2, 0x10); // all tx fifo
fifo_flush_rx(dwc2);
}

bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
Expand Down
Loading