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port_map.hpp
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#pragma once
//=========================================================================//
/*! @file
@brief RX64M, RX71M グループ・ポート・マッピング @n
・ペリフェラル型に従って、ポートの設定をグループ化して設定
@author 平松邦仁 (hira@rvf-rc45.net)
@copyright Copyright (C) 2016, 2024 Kunihito Hiramatsu @n
Released under the MIT license @n
https://github.com/hirakuni45/RX/blob/master/LICENSE
*/
//=========================================================================//
#include "RX64M/peripheral.hpp"
#include "RX64M/port.hpp"
#include "RX64M/mpc.hpp"
#include "RX600/port_map_order.hpp"
#if defined(SIG_RX64M) || defined(SIG_RX71M)
#else
#error "port_map.hpp requires SIG_RX64M or SIG_RX71M to be defined"
#endif
namespace device {
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief RX64M/RX71M ポート・マッピング・ユーティリティー
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
class port_map : public port_map_order {
static bool sci0_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD0: P21 RXD0/SMOSI0/SSDA0 (P21 LQFP176: 44)
// TXD0: P20 TXD0/SMISO0/SSCL0 (P20 LQFP176: 45)
// SCK0: P22 SCK0 (P22 LQFP176: 43)
PORT2::PMR.B1 = 0;
PORT2::PDR.B1 = i2c;
MPC::P21PFS.PSEL = sel; // ok
PORT2::PMR.B1 = enable;
PORT2::PMR.B0 = 0;
PORT2::ODR.B0 = i2c;
MPC::P20PFS.PSEL = sel; // ok
PORT2::PMR.B0 = enable;
if(spi) {
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel; // ok
PORT2::PMR.B2 = enable;
}
break;
case ORDER::SECOND:
// RXD0: P33 RXD0/SMISO0/SSCL0 (P33 LQFP176: 28)
// TXD0: P32 TXD0/SMOSI0/SSDA0 (P32 LQFP176: 29)
// SCK0: P34 SCK0 (P34 LQFP176: 27)
sel = enable ? 0b00'1011 : 0;
PORT3::PMR.B3 = 0;
PORT3::ODR.B3 = i2c;
MPC::P33PFS.PSEL = sel; // ok
PORT3::PMR.B3 = enable;
PORT3::PMR.B2 = 0;
PORT3::ODR.B2 = i2c;
MPC::P32PFS.PSEL = sel; // ok
PORT3::PMR.B2 = enable;
if(spi) {
PORT3::PMR.B4 = 0;
MPC::P34PFS.PSEL = sel; // ok
PORT3::PMR.B4 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci1_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD1: P15
// TXD1: P16
// SCK1: P17
PORT1::PMR.B5 = 0;
PORT1::PDR.B5 = i2c;
MPC::P15PFS.PSEL = sel; // ok
PORT1::PMR.B5 = enable;
PORT1::PMR.B6 = 0;
PORT1::ODR.B6 = i2c;
MPC::P16PFS.PSEL = sel; // ok
PORT1::PMR.B6 = enable;
if(spi) {
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = sel; // ok
PORT1::PMR.B7 = enable;
}
break;
case ORDER::SECOND: // Serial Boot Mode (145/144/100 pin)
// RXD1: P30
// TXD1: P26
// SCK1: P27
PORT3::PMR.B0 = 0;
PORT3::ODR.B0 = i2c;
MPC::P30PFS.PSEL = sel; // ok
PORT3::PMR.B0 = enable;
PORT2::PMR.B6 = 0;
PORT2::ODR.B6 = i2c;
MPC::P26PFS.PSEL = sel; // ok
PORT2::PMR.B6 = enable;
if(spi) {
PORT2::PMR.B7 = 0;
MPC::P27PFS.PSEL = sel; // ok
PORT2::PMR.B7 = enable;
}
break;
case ORDER::THIRD: // Serial Boot Mode (177/176 pin)
// RXD1: PF2
// TXD1: PF0
// SCK1: PF1
PORTF::PMR.B2 = 0;
PORTF::ODR.B2 = i2c;
MPC::PF2PFS.PSEL = sel; // ok
PORTF::PMR.B2 = enable;
PORTF::PMR.B0 = 0;
PORTF::ODR.B0 = i2c;
MPC::PF0PFS.PSEL = sel; // ok
PORTF::PMR.B0 = enable;
if(spi) {
PORTF::PMR.B1 = 0;
MPC::PF1PFS.PSEL = sel; // ok
PORTF::PMR.B1 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci2_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD2: P12 RXD2/SMOSI2/SSDA2 (P12 LQFP176: 53)
// TXD2: P13 TXD2/SMISO2/SSCL2 (P13 LQFP176: 52)
// SCK2: P11 SCK2 (P11 LQFP176: 67)
PORT1::PMR.B2 = 0;
PORT1::ODR.B2 = i2c;
MPC::P12PFS.PSEL = sel; // ok
PORT1::PMR.B2 = enable;
PORT1::PMR.B3 = 0;
PORT1::ODR.B3 = i2c;
MPC::P13PFS.PSEL = sel; // ok
PORT1::PMR.B3 = enable;
if(spi) {
PORT1::PMR.B1 = 0;
MPC::P11PFS.PSEL = sel; // ok
PORT1::PMR.B1 = enable;
}
break;
case ORDER::SECOND:
// RXD2: P52 RXD2/SMISO2/SSCL2 (P52 LQFP176: 70)
// TXD2: P50 TXD2/SMOSI2/SSDA2 (P50 LQFP176: 72)
// SCK2: P51 SCK2
PORT5::PMR.B2 = 0;
PORT5::ODR.B2 = i2c;
MPC::P52PFS.PSEL = sel; // ok
PORT5::PMR.B2 = enable;
PORT5::PMR.B0 = 0;
PORT5::ODR.B0 = i2c;
MPC::P50PFS.PSEL = sel; // ok
PORT5::PMR.B0 = enable;
if(spi) {
PORT5::PMR.B1 = 0;
MPC::P51PFS.PSEL = sel; // ok
PORT5::PMR.B1 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci3_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1011 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD3: P16 RXD3/SMISO3/SSCL3 (P16 LQFP176: 48)
// TXD3: P17 TXD3/SMOSI3/SSDA3 (P17 LQFP176: 46)
// SCK3: P15 SCK3 (P15 LQFP176: 50)
PORT1::PMR.B6 = 0;
PORT1::ODR.B6 = i2c;
MPC::P16PFS.PSEL = sel; // ok
PORT1::PMR.B6 = enable;
PORT1::PMR.B7 = 0;
PORT1::ODR.B7 = i2c;
MPC::P17PFS.PSEL = sel; // ok
PORT1::PMR.B7 = enable;
if(spi) {
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel; // ok
PORT1::PMR.B5 = enable;
}
break;
case ORDER::SECOND:
// RXD3: P25 RXD3/SMOSI3/SSDA3 (P25 LQFP176: 38)
// TXD3: P23 TXD3/SMISO3/SSCL3 (P23 LQFP176: 42)
// SCK3: P24 SCK3 (P24 LQFP176: 40)
sel = enable ? 0b00'1010 : 0; // ok
PORT2::PMR.B5 = 0;
PORT2::ODR.B5 = i2c;
MPC::P25PFS.PSEL = sel; // ok
PORT2::PMR.B5 = enable;
PORT2::PMR.B3 = 0;
PORT2::ODR.B3 = i2c;
MPC::P23PFS.PSEL = sel; // ok
PORT2::PMR.B3 = enable;
if(spi) {
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel; // ok
PORT2::PMR.B4 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci4_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD4: PB0 RXD4/SMOSI4/SSDA4 (PB0 LQFP176: 104)
// TXD4: PB1 TXD4/SMISO4/SSCL4 (PB1 LQFP176: 100)
// SCK4: PB3 SCK4 (PB3 LQFP176: 98)
PORTB::PMR.B0 = 0;
PORTB::ODR.B0 = i2c;
MPC::PB0PFS.PSEL = sel; // ok
PORTB::PMR.B0 = enable;
PORTB::PMR.B1 = 0;
PORTB::ODR.B1 = i2c;
MPC::PB1PFS.PSEL = sel; // ok
PORTB::PMR.B1 = enable;
if(spi) {
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel; // ok
PORTB::PMR.B3 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci5_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD5: PA2
// TXD5: PA4
// SCK5: PA1
PORTA::PMR.B2 = 0;
PORTA::ODR.B2 = i2c;
MPC::PA2PFS.PSEL = sel; // ok
PORTA::PMR.B2 = enable;
PORTA::PMR.B4 = 0;
PORTA::ODR.B4 = i2c;
MPC::PA4PFS.PSEL = sel; // ok
PORTA::PMR.B4 = enable;
if(spi) {
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel; // ok
PORTA::PMR.B1 = enable;
}
break;
case ORDER::SECOND:
// RXD5: PA3
// TXD5: PA4
// SCK5: PA1
PORTA::PMR.B3 = 0;
PORTA::ODR.B3 = i2c;
MPC::PA3PFS.PSEL = sel; // ok
PORTA::PMR.B3 = enable;
PORTA::PMR.B4 = 0;
PORTA::ODR.B4 = i2c;
MPC::PA4PFS.PSEL = sel; // ok
PORTA::PMR.B4 = enable;
if(spi) {
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel; // ok
PORTA::PMR.B1 = enable;
}
break;
case ORDER::THIRD:
// RXD5: PC2
// TXD5: PC3
// SCK5: PC1
PORTC::PMR.B2 = 0;
PORTC::ODR.B2 = i2c;
MPC::PC2PFS.PSEL = sel; // ok
PORTC::PMR.B2 = enable;
PORTC::PMR.B3 = 0;
PORTC::ODR.B3 = i2c;
MPC::PC3PFS.PSEL = sel; // ok
PORTC::PMR.B3 = enable;
if(spi) {
PORTC::PMR.B1 = 0;
MPC::PC1PFS.PSEL = sel; // ok
PORTC::PMR.B1 = enable;
}
break;
case ORDER::FOURTH:
// RXD5: PC2
// TXD5: PC3
// SCK5: PC4
PORTC::PMR.B2 = 0;
PORTC::ODR.B2 = i2c;
MPC::PC2PFS.PSEL = sel; // ok
PORTC::PMR.B2 = enable;
PORTC::PMR.B3 = 0;
PORTC::ODR.B3 = i2c;
MPC::PC3PFS.PSEL = sel; // ok
PORTC::PMR.B3 = enable;
if(spi) {
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel; // ok
PORTC::PMR.B4 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci6_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD6: P01 RXD6/SMOSI6/SSDA6 (P01 LQFP176: 7)
// TXD6: P00 TXD6/SMISO6/SSCL6 (P00 LQFP176: 8)
// SCK6: P02 SCK6 (P02 LQFP176: 6)
PORT0::PMR.B1 = 0;
PORT0::ODR.B1 = i2c;
MPC::P01PFS.PSEL = sel; // ok
PORT0::PMR.B1 = enable;
PORT0::PMR.B0 = 0;
PORT0::ODR.B0 = i2c;
MPC::P00PFS.PSEL = sel; // ok
PORT0::PMR.B0 = enable;
if(spi) {
PORT0::PMR.B2 = 0;
MPC::P02PFS.PSEL = sel; // ok
PORT0::PMR.B2 = enable;
}
break;
case ORDER::SECOND:
// RXD6: P33
// TXD6: P32
// SCK6: P34
PORT3::PMR.B3 = 0;
PORT3::ODR.B3 = i2c;
MPC::P33PFS.PSEL = sel; // ok
PORT3::PMR.B3 = enable;
PORT3::PMR.B2 = 0;
PORT3::ODR.B2 = i2c;
MPC::P32PFS.PSEL = sel; // ok
PORT3::PMR.B2 = enable;
if(spi) {
PORT3::PMR.B4 = 0;
MPC::P34PFS.PSEL = sel; // ok
PORT3::PMR.B4 = enable;
}
break;
case ORDER::THIRD:
// RXD6: PB0
// TXD6: PB1
// SCK6: PB3
sel = enable ? 0b0'1011 : 0;
PORTB::PMR.B0 = 0;
PORTB::ODR.B0 = i2c;
MPC::PB0PFS.PSEL = sel; // ok
PORTB::PMR.B0 = enable;
PORTB::PMR.B1 = 0;
PORTB::ODR.B1 = i2c;
MPC::PB1PFS.PSEL = sel; // ok
PORTB::PMR.B1 = enable;
if(spi) {
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel; // ok
PORTB::PMR.B3 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci7_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST: // GR-KAEDE J14 UART Lines
// RXD7: P92
// TXD7: P90
// SCK7: P91
PORT9::PMR.B2 = 0;
PORT9::ODR.B2 = i2c;
MPC::P92PFS.PSEL = sel; // ok
PORT9::PMR.B2 = enable;
PORT9::PMR.B0 = 0;
PORT9::ODR.B0 = i2c;
MPC::P90PFS.PSEL = sel; // ok
PORT9::PMR.B0 = enable;
if(spi) {
PORT9::PMR.B1 = 0;
MPC::P91PFS.PSEL = sel; // ok
PORT9::PMR.B1 = enable;
}
break;
default:
return false;
}
return true;
}
static bool scif8_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD8: PC6 RXD(F)8/SMOSI8/SSDA8 (PC6 LQFP176: 77)
// TXD8: PC7 TXD(F)8/SMISO8/SSCL8 (PC7 LQFP176: 76)
// SCK8: PC5 SCK8 (PC5 LQFP176: 78)
PORTC::PMR.B6 = 0;
PORTC::ODR.B6 = i2c;
MPC::PC6PFS.PSEL = sel; // ok
PORTC::PMR.B6 = enable;
PORTC::PMR.B7 = 0;
PORTC::ODR.B7 = i2c;
MPC::PC7PFS.PSEL = sel; // ok
PORTC::PMR.B7 = enable;
if(spi) {
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel; // ok
PORTC::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool scif9_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD9: PB6 RXD(F)9/SMOSI9/SSDA9 (PB6 LQFP176: 95)
// TXD9: PB7 TXD(F)9/SMISO9/SSCL9 (PB7 LQFP176: 94)
// SCK9: PB5 SCK9 (PB5 LQFP176: 96)
PORTB::PMR.B6 = 0;
PORTB::ODR.B6 = i2c;
MPC::PB6PFS.PSEL = sel; // ok
PORTB::PMR.B6 = enable;
PORTB::PMR.B7 = 0;
PORTB::ODR.B7 = i2c;
MPC::PB7PFS.PSEL = sel; // ok
PORTB::PMR.B7 = enable;
if(spi) {
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel; // ok
PORTB::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool scif10_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD10: P81
// TXD10: P82
// SCK10: P80
PORTB::PMR.B1 = 0;
PORTB::ODR.B1 = i2c;
MPC::PB1PFS.PSEL = sel; // ok
PORTB::PMR.B1 = enable;
PORTB::PMR.B2 = 0;
PORTB::ODR.B2 = i2c;
MPC::PB2PFS.PSEL = sel; // ok
PORTB::PMR.B2 = enable;
if(spi) {
PORT8::PMR.B0 = 0;
MPC::P80PFS.PSEL = sel; // ok
PORT8::PMR.B0 = enable;
}
break;
case ORDER::SECOND:
// RXD10: P86
// TXD10: P87
// SCK10: P83
PORT8::PMR.B6 = 0;
PORT8::ODR.B6 = i2c;
MPC::P86PFS.PSEL = sel; // ok
PORT8::PMR.B6 = enable;
PORT8::PMR.B7 = 0;
PORT8::ODR.B7 = i2c;
MPC::P87PFS.PSEL = sel; // ok
PORT8::PMR.B7 = enable;
if(spi) {
PORT8::PMR.B3 = 0;
MPC::P83PFS.PSEL = sel; // ok
PORT8::PMR.B3 = enable;
}
break;
default:
return false;
}
return true;
}
static bool scif11_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD11: P76 RXD(F)11/SMOSI11/SSDA11 (P76 LQFP176: 85)
// TXD11: P77 TXD(F)11/SMISO11/SSCL11 (P77 LQFP176: 84)
// SCK11: P75 SCK11 (P75 LQFP176: 87)
PORT7::PMR.B6 = 0;
PORT7::ODR.B6 = i2c;
MPC::P76PFS.PSEL = sel; // ok
PORT7::PMR.B6 = enable;
PORT7::PMR.B7 = 0;
PORT7::ODR.B7 = i2c;
MPC::P77PFS.PSEL = sel; // ok
PORT7::PMR.B7 = enable;
if(spi) {
PORT7::PMR.B5 = 0;
MPC::P75PFS.PSEL = sel; // ok
PORT7::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci12_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1100 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD12: PE2 RXD12/SMISO12/SSCL12 (PE2 LQFP176: 133)
// TXD12: PE1 TXD12/SMOSI12/SSDA12 (PE1 LQFP176: 134)
// SCK12: PE0 SCK12 (PE0 LQFP176: 135)
PORTE::PMR.B2 = 0;
PORTE::ODR.B2 = i2c;
MPC::PE2PFS.PSEL = sel; // ok
PORTE::PMR.B2 = enable;
PORTE::PMR.B1 = 0;
PORTE::ODR.B1 = i2c;
MPC::PE1PFS.PSEL = sel; // ok
PORTE::PMR.B1 = enable;
if(spi) {
PORTE::PMR.B0 = 0;
MPC::PE0PFS.PSEL = sel; // ok
PORTE::PMR.B0 = enable;
}
break;
default:
return false;
}
return true;
}
static bool riic0_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b00'1111 : 0;
switch(odr) {
case ORDER::FIRST:
// SCL0: P12 SCL0 (P12 LQFP176: 53)
// SDA0: P13 SDA0 (P13 LQFP176: 52)
PORT1::PMR.B2 = 0;
MPC::P12PFS.PSEL = sel; // ok
PORT1::PMR.B2 = enable;
PORT1::PMR.B3 = 0;
MPC::P13PFS.PSEL = sel; // ok
PORT1::PMR.B3 = enable;
break;
default:
return false;
}
return true;
}
static bool riic2_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b00'1111 : 0;
switch(odr) {
case ORDER::FIRST:
// SCL2: P16 SCL2 (P16 LQFP176: 48)
// SDA2: P17 SDA2 (P17 LQFP176: 46)
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = sel; // ok
PORT1::PMR.B6 = enable;
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = sel; // ok
PORT1::PMR.B7 = enable;
break;
default:
return false;
}
return true;
}
static bool can0_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b01'0000 : 0;
switch(odr) {
case ORDER::FIRST:
// CRX0: P33 CRX0 (P33 LQFP176: 28)
// CTX0: P32 CTX0 (P32 LQFP176: 29)
PORT3::PMR.B3 = 0;
MPC::P33PFS.PSEL = sel; // ok
PORT3::PMR.B3 = enable;
PORT3::PMR.B2 = 0;
MPC::P32PFS.PSEL = sel; // ok
PORT3::PMR.B2 = enable;
break;
case ORDER::SECOND:
// CRX0: PD2 CRX0 (PD2 LQFP176: 154)
// CTX0: PD1 CTX0 (PD1 LQFP176: 156)
PORTD::PMR.B2 = 0;
MPC::PD2PFS.PSEL = sel; // ok
PORTD::PMR.B2 = enable;
PORTD::PMR.B1 = 0;
MPC::PD1PFS.PSEL = sel; // ok
PORTD::PMR.B1 = enable;
break;
default:
return false;
}
return true;
}
static bool can1_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b01'0000 : 0;
switch(odr) {
case ORDER::FIRST:
// CRX1: P15 CRX1-DS (P15 LQFP176: 50)
// CTX1: P14 CTX1 (P14 LQFP176: 51)
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel; // ok
PORT1::PMR.B5 = enable;
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = sel; // ok
PORT1::PMR.B4 = enable;
break;
case ORDER::SECOND:
// CRX1: P55 CRX1 (P55 LQFP176: 65)
// CTX1: P54 CTX1 (P54 LQFP176: 66)
PORT5::PMR.B5 = 0;
MPC::P55PFS.PSEL = sel; // ok
PORT5::PMR.B5 = enable;
PORT5::PMR.B4 = 0;
MPC::P54PFS.PSEL = sel; // ok
PORT5::PMR.B4 = enable;
break;
default:
return false;
}
return true;
}
static bool can2_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b01'0000 : 0;
switch(odr) {
case ORDER::FIRST:
// CRX2: P67 CRX2 (P67 LQFP176: 120)
// CTX2: P66 CTX2 (P66 LQFP176: 122)
PORT6::PMR.B7 = 0;
MPC::P67PFS.PSEL = sel; // ok
PORT6::PMR.B7 = enable;
PORT6::PMR.B6 = 0;
MPC::P66PFS.PSEL = sel; // ok
PORT6::PMR.B6 = enable;
break;
default:
return false;
}
return true;
}
static bool rspi0_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b00'1101 : 0;
switch(odr) {
case ORDER::FIRST:
// RSPCKA: PA5 RSPCKA-B (PA5 LQFP176: 108)
// MOSIA: PA6 MOSIA-B (PA6 LQFP176: 107)
// MISOA: PA7 MISOA-B (PA7 LQFP176: 106)
PORTA::PMR.B5 = 0;
MPC::PA5PFS.PSEL = sel; // ok
PORTA::PMR.B5 = enable;
PORTA::PMR.B6 = 0;
MPC::PA6PFS.PSEL = sel; // ok
PORTA::PMR.B6 = enable;
PORTA::PMR.B7 = 0;
MPC::PA7PFS.PSEL = sel; // ok
PORTA::PMR.B7 = enable;
break;
case ORDER::SECOND:
// RSPCKA: PC5 RSPCKA-A (PC5 LQFP176: 78)
// MOSIA: PC6 MOSIA-A (PC6 LQFP176: 77)
// MISOA: PC7 MISOA-A (PC7 LQFP176: 76)
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel; // ok
PORTC::PMR.B5 = enable;
PORTC::PMR.B6 = 0;
MPC::PC6PFS.PSEL = sel; // ok
PORTC::PMR.B6 = enable;
PORTC::PMR.B7 = 0;
MPC::PC7PFS.PSEL = sel; // ok
PORTC::PMR.B7 = enable;
break;
default:
return false;
}
return true;
}
#if defined(SIG_RX71M)
static bool rspi1_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b00'1101 : 0;
switch(odr) {
case ORDER::FIRST:
// RSPCKB: P27
// MOSIB: P26
// MISOB: P30
PORT2::PMR.B7 = 0;
MPC::P27PFS.PSEL = sel; // ok
PORT2::PMR.B7 = enable;
PORT2::PMR.B6 = 0;
MPC::P26PFS.PSEL = sel; // ok
PORT2::PMR.B6 = enable;
PORT3::PMR.B0 = 0;
MPC::P30PFS.PSEL = sel; // ok
PORT3::PMR.B0 = enable;
break;
case ORDER::SECOND:
// RSPCKB: PE5
// MOSIB: PE6
// MISOB: PE7
PORTE::PMR.B5 = 0;
MPC::PE5PFS.PSEL = sel; // ok
PORTE::PMR.B5 = enable;
PORTE::PMR.B6 = 0;
MPC::PE6PFS.PSEL = sel; // ok
PORTE::PMR.B6 = enable;
PORTE::PMR.B7 = 0;
MPC::PE7PFS.PSEL = sel; // ok
PORTE::PMR.B7 = enable;
break;
default:
return false;
}
return true;
}
#endif
static bool usb0_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b01'0011 : 0;
switch(odr) {
case ORDER::FIRST: // USB0 Host: VBUSEN, OVRCURB
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel; // USB0_VBUSEN (P24 LQFP176: 40)
PORT2::PMR.B4 = enable;
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel; // USB0_OVRCURB (P22 LQFP176: 43)
PORT2::PMR.B2 = enable;
break;
default:
return false;
}
return true;
}
static bool cmtw0_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
switch(odr) {
case ORDER::FIRST:
if(opt == OPTIONAL::CMTW_TOC0) {
// TOC0: PC7
PORTC::PMR.B7 = 0;
MPC::PC7PFS.PSEL = enable ? 0b01'1101 : 0;
PORTC::PMR.B7 = enable;
} else if(opt == OPTIONAL::CMTW_TIC0) {
// TIC0: PC6
PORTC::PMR.B6 = 0;
MPC::PC6PFS.PSEL = enable ? 0b01'1101 : 0;
PORTC::PMR.B6 = enable;
} else if(opt == OPTIONAL::CMTW_TOC1) {
// TOC1: PE7
PORTE::PMR.B7 = 0;
MPC::PE7PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B7 = enable;
} else if(opt == OPTIONAL::CMTW_TIC1) {
// TIC1: PE6
PORTE::PMR.B6 = 0;
MPC::PE6PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B6 = enable;
} else {
return false;
}
break;
default:
return false;
}
return true;
}
static bool cmtw1_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
switch(odr) {
case ORDER::FIRST:
if(opt == OPTIONAL::CMTW_TOC0) {
// TOC2: PD3
PORTD::PMR.B3 = 0;
MPC::PD3PFS.PSEL = enable ? 0b01'1101 : 0;
PORTD::PMR.B3 = enable;
} else if(opt == OPTIONAL::CMTW_TIC0) {
// TIC2: PD2
PORTD::PMR.B2 = 0;
MPC::PD2PFS.PSEL = enable ? 0b01'1101 : 0;
PORTD::PMR.B2 = enable;
} else if(opt == OPTIONAL::CMTW_TOC1) {
// TOC3: PE3
PORTE::PMR.B3 = 0;
MPC::PE3PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B3 = enable;
} else if(opt == OPTIONAL::CMTW_TIC1) {
// TIC3: PE2
PORTE::PMR.B2 = 0;
MPC::PE2PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B2 = enable;
} else {
return false;
}
break;
default:
return false;
}
return true;
}
static bool sdhi_1st_(SDHI_STATE state) noexcept
{
bool ret = true;
bool enable = true;
uint8_t sel = enable ? 0b011010 : 0;
switch(state) {
case SDHI_STATE::START:
PORT8::PMR.B0 = 0;
MPC::P80PFS.PSEL = sel; // SDHI_WP (81)
PORT8::PMR.B0 = enable;
PORT8::PMR.B1 = 0;
MPC::P81PFS.PSEL = sel; // SDHI_CD (80)
PORT8::PMR.B1 = enable;
break;
case SDHI_STATE::EJECT:
enable = 0;
sel = 0;
case SDHI_STATE::INSERT:
PORTC::PMR.B2 = 0;
MPC::PC2PFS.PSEL = sel; // SDHI_D3 (86)
PORTC::PMR.B2 = enable;
PORTC::PMR.B3 = 0;
MPC::PC3PFS.PSEL = sel; // SDHI_D0 (83)
PORTC::PMR.B3 = enable;
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel; // SDHI_D1 (82)
PORTC::PMR.B4 = enable;
PORT7::PMR.B5 = 0;
MPC::P75PFS.PSEL = sel; // SDHI_D2 (87)
PORT7::PMR.B5 = enable;
PORT7::PMR.B6 = 0;
MPC::P76PFS.PSEL = sel; // SDHI_CMD (85)
PORT7::PMR.B6 = enable;
PORT7::PMR.B7 = 0;
MPC::P77PFS.PSEL = sel; // SDHI_CLK (84)
PORT7::PMR.B7 = enable;
break;
case SDHI_STATE::DESTROY:
sel = 0;
PORT8::PMR.B0 = 0;
MPC::P80PFS.PSEL = sel; // SDHI_WP (81)
PORT8::PMR.B1 = 0;
MPC::P81PFS.PSEL = sel; // SDHI_CD (80)
PORTC::PMR.B2 = 0;
MPC::PC2PFS.PSEL = sel; // SDHI_D3 (86)
PORTC::PMR.B3 = 0;
MPC::PC3PFS.PSEL = sel; // SDHI_D0 (83)
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel; // SDHI_D1 (82)
PORT7::PMR.B5 = 0;
MPC::P75PFS.PSEL = sel; // SDHI_D2 (87)
PORT7::PMR.B6 = 0;
MPC::P76PFS.PSEL = sel; // SDHI_CMD (85)
PORT7::PMR.B7 = 0;
MPC::P77PFS.PSEL = sel; // SDHI_CLK (84)
break;
default:
ret = false;
}
return ret;
}
static inline USER_FUNC_TYPE user_func_;
public: