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Pipelined-RISC-V-Processor
Pipelined-RISC-V-Processor PublicA fully pipelined risc-v processor implemented in verilog and tested on an FPGA board
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listeners
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Get processes listening on a TCP port in a cross-platform way
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Boolean-Functions-Simplifier
Boolean-Functions-Simplifier PublicForked from GehadSalemFekry/Boolean-Functions-Simplifier
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Digtal-Clock-Alarm
Digtal-Clock-Alarm PublicForked from GehadSalemFekry/Digtal-Clock-Alarm
A Digital Clock/Alarm System implemented using Verilog. The project was created using Vivado software and implemented on the Basys 3 FPGA board. This project was created for the Digital Desgin I Co…
Verilog
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