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oxford-semi.lbr
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<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="6.4">
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<library>
<description><b>Oxford Semiconductors</b><p>
<p>THIS LIBRARY IS PROVIDED AS IS AND WITHOUT WARRANTY OF ANY KIND, EXPRESSED OR IMPLIED.<br>
USE AT YOUR OWN RISK!<p>
<author>Copyright (C) 2008, Bob Starr<br> http://www.bobstarr.net<br></author></description>
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</packages>
<symbols>
<symbol name="OXFW971">
<wire x1="-55.88" y1="55.88" x2="55.88" y2="55.88" width="0.4064" layer="94"/>
<wire x1="55.88" y1="55.88" x2="55.88" y2="-55.88" width="0.4064" layer="94"/>
<wire x1="55.88" y1="-55.88" x2="-55.88" y2="-55.88" width="0.4064" layer="94"/>
<wire x1="-55.88" y1="-55.88" x2="-55.88" y2="55.88" width="0.4064" layer="94"/>
<text x="-56.515" y="57.15" size="1.778" layer="95">>NAME</text>
<text x="-55.88" y="-59.055" size="1.778" layer="96">>VALUE</text>
<pin name="FLASH_EXHV@1" x="-60.96" y="33.02" length="middle" direction="pwr"/>
<pin name="FLASH_VCCF@2" x="-60.96" y="30.48" length="middle" direction="pwr"/>
<pin name="FLASH_VCC3F@3" x="-60.96" y="27.94" length="middle" direction="pwr"/>
<pin name="JTAG_TDI" x="-60.96" y="25.4" length="middle"/>
<pin name="JTAG_TCLK" x="-60.96" y="22.86" length="middle" direction="in"/>
<pin name="JTAG_TMS" x="-60.96" y="20.32" length="middle" direction="in"/>
<pin name="I2C_SCL" x="-60.96" y="17.78" length="middle"/>
<pin name="TEST_MODE2" x="-60.96" y="15.24" length="middle" direction="in"/>
<pin name="FLASH_VSSF@9" x="-60.96" y="12.7" length="middle" direction="pwr"/>
<pin name="FLASH_VSSL@10" x="-60.96" y="10.16" length="middle" direction="pwr"/>
<pin name="FLASH_VCCL@11" x="-60.96" y="7.62" length="middle" direction="pwr"/>
<pin name="I2C_SDA" x="-60.96" y="5.08" length="middle"/>
<pin name="IR_RX" x="-60.96" y="2.54" length="middle"/>
<pin name="PWM0" x="-60.96" y="0" length="middle"/>
<pin name="JTAG_UART_SEL" x="-60.96" y="-2.54" length="middle" direction="in"/>
<pin name="VDD1V8@16" x="-60.96" y="-5.08" length="middle" direction="pwr"/>
<pin name="VSS1V8@17" x="-60.96" y="-7.62" length="middle" direction="pwr"/>
<pin name="PWM3" x="-60.96" y="-10.16" length="middle"/>
<pin name="PWM2" x="-60.96" y="-12.7" length="middle"/>
<pin name="PWM1" x="-60.96" y="-15.24" length="middle"/>
<pin name="AUDIO1_NFS_CLK_OUT@21" x="-60.96" y="-17.78" length="middle"/>
<pin name="VDD3V3@22" x="-60.96" y="-20.32" length="middle" direction="pwr"/>
<pin name="VSS3V3@23" x="-60.96" y="-22.86" length="middle" direction="pwr"/>
<pin name="Z_FORCE_FLASH" x="-60.96" y="-25.4" length="middle" direction="in"/>
<pin name="Z_RESET" x="-60.96" y="-27.94" length="middle" direction="in"/>
<pin name="LINK_PD7" x="-30.48" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_PD6" x="-27.94" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_PD5" x="-25.4" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_PD4" x="-22.86" y="-60.96" length="middle" rot="R90"/>
<pin name="VDD3V3@30" x="-20.32" y="-60.96" length="middle" direction="pwr" rot="R90"/>
<pin name="VSS3V3@31" x="-17.78" y="-60.96" length="middle" direction="pwr" rot="R90"/>
<pin name="LINK_PD3" x="-15.24" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_PD2" x="-12.7" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_PD1" x="-10.16" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_PD0" x="-7.62" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_CTL1" x="-5.08" y="-60.96" length="middle" rot="R90"/>
<pin name="LINK_CTL0" x="-2.54" y="-60.96" length="middle" rot="R90"/>
<pin name="VDD1V8@38" x="0" y="-60.96" length="middle" direction="pwr" rot="R90"/>
<pin name="VSS1V8@39" x="2.54" y="-60.96" length="middle" direction="pwr" rot="R90"/>
<pin name="LINK_LCLK" x="5.08" y="-60.96" length="middle" direction="out" rot="R90"/>
<pin name="LINK_PCLK" x="7.62" y="-60.96" length="middle" direction="in" rot="R90"/>
<pin name="LINK_LREQ" x="10.16" y="-60.96" length="middle" direction="out" rot="R90"/>
<pin name="LINK_LINK_ON" x="12.7" y="-60.96" length="middle" direction="in" rot="R90"/>
<pin name="LINK_PINT" x="15.24" y="-60.96" length="middle" direction="in" rot="R90"/>
<pin name="LINK_LPS" x="17.78" y="-60.96" length="middle" direction="out" rot="R90"/>
<pin name="VSS3V3@47" x="22.86" y="-60.96" length="middle" direction="pwr" rot="R90"/>
<pin name="VDD3V3@46" x="20.32" y="-60.96" length="middle" direction="pwr" rot="R90"/>
<pin name="VDD3V3@50" x="30.48" y="-60.96" length="middle" direction="pwr" rot="R90"/>
<pin name="AUDIO1_TX_DO" x="25.4" y="-60.96" length="middle" rot="R90"/>
<pin name="AUDIO1_TX_BIT_CLK" x="27.94" y="-60.96" length="middle" rot="R90"/>
<pin name="AUDIO1_RX_BIT_CLK" x="60.96" y="-27.94" length="middle" rot="R180"/>
<pin name="AUDIO2_TX_BIT_CLK" x="60.96" y="-25.4" length="middle" rot="R180"/>
<pin name="AUDIO2_RX_BIT_CLK" x="60.96" y="-22.86" length="middle" rot="R180"/>
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<pin name="AUDIO2_TX_D1" x="60.96" y="-17.78" length="middle" direction="out" rot="R180"/>
<pin name="VSS3V3@56" x="60.96" y="-15.24" length="middle" direction="pwr" rot="R180"/>
<pin name="AUDIO2_TX_D2" x="60.96" y="-12.7" length="middle" direction="out" rot="R180"/>
<pin name="AUDIO2_TX_D3" x="60.96" y="-10.16" length="middle" direction="out" rot="R180"/>
<pin name="AUDIO2_RX_D0" x="60.96" y="-7.62" length="middle" rot="R180"/>
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<pin name="VSS1V8@64" x="60.96" y="5.08" length="middle" direction="pwr" rot="R180"/>
<pin name="SYS_FS_PDOUT" x="60.96" y="7.62" length="middle" rot="R180"/>
<pin name="VCO_FS_PDOUT" x="60.96" y="10.16" length="middle" rot="R180"/>
<pin name="AUDIO2_TX_WORD_CLK" x="60.96" y="12.7" length="middle" rot="R180"/>
<pin name="AUDIO1_TX_WORD_CLK" x="60.96" y="15.24" length="middle" rot="R180"/>
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<pin name="AUDIO1_RX_WORD_CLK" x="60.96" y="20.32" length="middle" rot="R180"/>
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<pin name="VSS3V3@72" x="60.96" y="25.4" length="middle" direction="pwr" rot="R180"/>
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<pin name="AUDIO1_RX_D3" x="60.96" y="33.02" length="middle" rot="R180"/>
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<pin name="AUDIO1_TX_D2" x="27.94" y="60.96" length="middle" direction="out" rot="R270"/>
<pin name="AUDIO1_RX_D2" x="25.4" y="60.96" length="middle" rot="R270"/>
<pin name="AUDIO1_RX_D1" x="22.86" y="60.96" length="middle" rot="R270"/>
<pin name="AUDIO1_RX_D0" x="20.32" y="60.96" length="middle" rot="R270"/>
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<pin name="VDD3V3@83" x="12.7" y="60.96" length="middle" direction="pwr" rot="R270"/>
<pin name="AUDIO_NFS_CLK_IN" x="10.16" y="60.96" length="middle" direction="in" rot="R270"/>
<pin name="AUDIO1_NFS_CLK_OUT@85" x="7.62" y="60.96" length="middle" rot="R270"/>
<pin name="TEST_MODE1" x="5.08" y="60.96" length="middle" direction="in" rot="R270"/>
<pin name="VSS1V8@87" x="2.54" y="60.96" length="middle" direction="pwr" rot="R270"/>
<pin name="VDD1V8@88" x="0" y="60.96" length="middle" direction="pwr" rot="R270"/>
<pin name="VBB_PLL@89" x="-2.54" y="60.96" length="middle" direction="pas" rot="R270"/>
<pin name="PLL2073_AVSS@90" x="-5.08" y="60.96" length="middle" direction="pwr" rot="R270"/>
<pin name="PLL2073_DVDD@91" x="-7.62" y="60.96" length="middle" direction="pwr" rot="R270"/>
<pin name="PLL2073_AVDD@92" x="-10.16" y="60.96" length="middle" direction="pwr" rot="R270"/>
<pin name="PLL2073_DVSS@93" x="-12.7" y="60.96" length="middle" direction="pwr" rot="R270"/>
<pin name="UART2_SOUT" x="-15.24" y="60.96" length="middle" rot="R270"/>
<pin name="UART2_SIN" x="-17.78" y="60.96" length="middle" rot="R270"/>
<pin name="VSS3V3" x="-20.32" y="60.96" length="middle" rot="R270"/>
<pin name="VDD3V3" x="-22.86" y="60.96" length="middle" rot="R270"/>
<pin name="SEL_B_PHY" x="-25.4" y="60.96" length="middle" direction="in" rot="R270"/>
<pin name="TEST_MODE0" x="-27.94" y="60.96" length="middle" direction="in" rot="R270"/>
<pin name="JTAG_TDO" x="-30.48" y="60.96" length="middle" direction="out" rot="R270"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="OXFW971" prefix="U">
<description>Firewire Audio Controller<p>
16 Channel, Isochronous Streaming, S/PDIF & MIDI</description>
<gates>
<gate name="G$1" symbol="OXFW971" x="0" y="0"/>
</gates>
<devices>
<device name="TQ" package="TQFP100">
<connects>
<connect gate="G$1" pin="AUDIO1_NFS_CLK_OUT@21" pad="21"/>
<connect gate="G$1" pin="AUDIO1_NFS_CLK_OUT@85" pad="85"/>
<connect gate="G$1" pin="AUDIO1_RX_BIT_CLK" pad="51"/>
<connect gate="G$1" pin="AUDIO1_RX_D0" pad="80"/>
<connect gate="G$1" pin="AUDIO1_RX_D1" pad="79"/>
<connect gate="G$1" pin="AUDIO1_RX_D2" pad="78"/>
<connect gate="G$1" pin="AUDIO1_RX_D3" pad="75"/>
<connect gate="G$1" pin="AUDIO1_RX_WORD_CLK" pad="70"/>
<connect gate="G$1" pin="AUDIO1_TX_BIT_CLK" pad="49"/>
<connect gate="G$1" pin="AUDIO1_TX_D1" pad="81"/>
<connect gate="G$1" pin="AUDIO1_TX_D2" pad="77"/>
<connect gate="G$1" pin="AUDIO1_TX_D3" pad="76"/>
<connect gate="G$1" pin="AUDIO1_TX_DO" pad="48"/>
<connect gate="G$1" pin="AUDIO1_TX_WORD_CLK" pad="68"/>
<connect gate="G$1" pin="AUDIO2_RX_BIT_CLK" pad="53"/>
<connect gate="G$1" pin="AUDIO2_RX_D0" pad="59"/>
<connect gate="G$1" pin="AUDIO2_RX_D1" pad="60"/>
<connect gate="G$1" pin="AUDIO2_RX_D2" pad="61"/>
<connect gate="G$1" pin="AUDIO2_RX_D3" pad="62"/>
<connect gate="G$1" pin="AUDIO2_RX_WORD_CLK" pad="69"/>
<connect gate="G$1" pin="AUDIO2_TX_BIT_CLK" pad="52"/>
<connect gate="G$1" pin="AUDIO2_TX_D0" pad="54"/>
<connect gate="G$1" pin="AUDIO2_TX_D1" pad="55"/>
<connect gate="G$1" pin="AUDIO2_TX_D2" pad="57"/>
<connect gate="G$1" pin="AUDIO2_TX_D3" pad="58"/>
<connect gate="G$1" pin="AUDIO2_TX_WORD_CLK" pad="67"/>
<connect gate="G$1" pin="AUDIO_NFS_CLK_IN" pad="84"/>
<connect gate="G$1" pin="FLASH_EXHV@1" pad="1"/>
<connect gate="G$1" pin="FLASH_VCC3F@3" pad="3"/>
<connect gate="G$1" pin="FLASH_VCCF@2" pad="2"/>
<connect gate="G$1" pin="FLASH_VCCL@11" pad="11"/>
<connect gate="G$1" pin="FLASH_VSSF@9" pad="9"/>
<connect gate="G$1" pin="FLASH_VSSL@10" pad="10"/>
<connect gate="G$1" pin="I2C_SCL" pad="7"/>
<connect gate="G$1" pin="I2C_SDA" pad="12"/>
<connect gate="G$1" pin="IR_RX" pad="13"/>
<connect gate="G$1" pin="JTAG_TCLK" pad="5"/>
<connect gate="G$1" pin="JTAG_TDI" pad="4"/>
<connect gate="G$1" pin="JTAG_TDO" pad="100"/>
<connect gate="G$1" pin="JTAG_TMS" pad="6"/>
<connect gate="G$1" pin="JTAG_UART_SEL" pad="15"/>
<connect gate="G$1" pin="LINK_CTL0" pad="37"/>
<connect gate="G$1" pin="LINK_CTL1" pad="36"/>
<connect gate="G$1" pin="LINK_LCLK" pad="40"/>
<connect gate="G$1" pin="LINK_LINK_ON" pad="43"/>
<connect gate="G$1" pin="LINK_LPS" pad="45"/>
<connect gate="G$1" pin="LINK_LREQ" pad="42"/>
<connect gate="G$1" pin="LINK_PCLK" pad="41"/>
<connect gate="G$1" pin="LINK_PD0" pad="35"/>
<connect gate="G$1" pin="LINK_PD1" pad="34"/>
<connect gate="G$1" pin="LINK_PD2" pad="33"/>
<connect gate="G$1" pin="LINK_PD3" pad="32"/>
<connect gate="G$1" pin="LINK_PD4" pad="29"/>
<connect gate="G$1" pin="LINK_PD5" pad="28"/>
<connect gate="G$1" pin="LINK_PD6" pad="27"/>
<connect gate="G$1" pin="LINK_PD7" pad="26"/>
<connect gate="G$1" pin="LINK_PINT" pad="44"/>
<connect gate="G$1" pin="PLL2073_AVDD@92" pad="92"/>
<connect gate="G$1" pin="PLL2073_AVSS@90" pad="90"/>
<connect gate="G$1" pin="PLL2073_DVDD@91" pad="91"/>
<connect gate="G$1" pin="PLL2073_DVSS@93" pad="93"/>
<connect gate="G$1" pin="PWM0" pad="14"/>
<connect gate="G$1" pin="PWM1" pad="20"/>
<connect gate="G$1" pin="PWM2" pad="19"/>
<connect gate="G$1" pin="PWM3" pad="18"/>
<connect gate="G$1" pin="SEL_B_PHY" pad="98"/>
<connect gate="G$1" pin="SYS_FS_PDOUT" pad="65"/>
<connect gate="G$1" pin="TEST_MODE0" pad="99"/>
<connect gate="G$1" pin="TEST_MODE1" pad="86"/>
<connect gate="G$1" pin="TEST_MODE2" pad="8"/>
<connect gate="G$1" pin="UART2_SIN" pad="95"/>
<connect gate="G$1" pin="UART2_SOUT" pad="94"/>
<connect gate="G$1" pin="UART3_SIN" pad="74"/>
<connect gate="G$1" pin="UART3_SOUT" pad="73"/>
<connect gate="G$1" pin="VBB_PLL@89" pad="89"/>
<connect gate="G$1" pin="VCO_FS_PDOUT" pad="66"/>
<connect gate="G$1" pin="VDD1V8@16" pad="16"/>
<connect gate="G$1" pin="VDD1V8@38" pad="38"/>
<connect gate="G$1" pin="VDD1V8@63" pad="63"/>
<connect gate="G$1" pin="VDD1V8@88" pad="88"/>
<connect gate="G$1" pin="VDD3V3" pad="97"/>
<connect gate="G$1" pin="VDD3V3@22" pad="22"/>
<connect gate="G$1" pin="VDD3V3@30" pad="30"/>
<connect gate="G$1" pin="VDD3V3@46" pad="46"/>
<connect gate="G$1" pin="VDD3V3@50" pad="50"/>
<connect gate="G$1" pin="VDD3V3@71" pad="71"/>
<connect gate="G$1" pin="VDD3V3@83" pad="83"/>
<connect gate="G$1" pin="VSS1V8@17" pad="17"/>
<connect gate="G$1" pin="VSS1V8@39" pad="39"/>
<connect gate="G$1" pin="VSS1V8@64" pad="64"/>
<connect gate="G$1" pin="VSS1V8@87" pad="87"/>
<connect gate="G$1" pin="VSS3V3" pad="96"/>
<connect gate="G$1" pin="VSS3V3@23" pad="23"/>
<connect gate="G$1" pin="VSS3V3@31" pad="31"/>
<connect gate="G$1" pin="VSS3V3@47" pad="47"/>
<connect gate="G$1" pin="VSS3V3@56" pad="56"/>
<connect gate="G$1" pin="VSS3V3@72" pad="72"/>
<connect gate="G$1" pin="VSS3V3@82" pad="82"/>
<connect gate="G$1" pin="Z_FORCE_FLASH" pad="24"/>
<connect gate="G$1" pin="Z_RESET" pad="25"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>