From 000d751d9611ea8f5b6edc461e455c3061846836 Mon Sep 17 00:00:00 2001 From: Hanh Ha Date: Sun, 5 Apr 2020 20:53:59 +0700 Subject: [PATCH] Add support for logic type and fix minor syntax error --- hdlparse/minilexer.py | 2 +- hdlparse/verilog_parser.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hdlparse/minilexer.py b/hdlparse/minilexer.py index 30121ae..b60efe3 100644 --- a/hdlparse/minilexer.py +++ b/hdlparse/minilexer.py @@ -33,7 +33,7 @@ def __init__(self, tokens, flags=re.MULTILINE): if new_state and new_state.startswith('#pop'): try: new_state = -int(new_state.split(':')[1]) - except IndexError, ValueError: + except (IndexError, ValueError): new_state = -1 full_patterns.append((pat, action, new_state)) diff --git a/hdlparse/verilog_parser.py b/hdlparse/verilog_parser.py index df05a81..1e2bfdc 100644 --- a/hdlparse/verilog_parser.py +++ b/hdlparse/verilog_parser.py @@ -17,7 +17,7 @@ ], 'module': [ (r'parameter\s*(signed|integer|realtime|real|time)?\s*(\[[^]]+\])?', 'parameter_start', 'parameters'), - (r'(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start', 'module_port'), + (r'(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start', 'module_port'), (r'endmodule', 'end_module', '#pop'), (r'/\*', 'block_comment', 'block_comment'), (r'//#\s*{{(.*)}}\n', 'section_meta'), @@ -30,7 +30,7 @@ (r'[);]', None, '#pop'), ], 'module_port': [ - (r'\s*(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start'), + (r'\s*(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start'), (r'\s*(\w+)\s*,?', 'port_param'), (r'[);]', None, '#pop'), (r'//#\s*{{(.*)}}\n', 'section_meta'),