@@ -32,11 +32,13 @@ def write(self, value=0, **kwargs):
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def read (self , ** kwargs ): return self .adev .rreg (self .reg_off ) & self ._parse_kwargs (** kwargs )[0 ]
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class AMFirmware :
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- def __init__ (self ):
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+ def __init__ (self , adev ):
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+ def fmt_ver (hwip ): return f"{ adev .ip_versions [hwip ]// 10000 } _{ (adev .ip_versions [hwip ]// 100 )% 100 } _{ adev .ip_versions [hwip ]% 100 } "
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+
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# Load SOS firmware
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self .sos_fw = {}
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- blob , sos_hdr = self .load_fw ("psp_13_0_0_sos .bin" , am .struct_psp_firmware_header_v2_0 )
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+ blob , sos_hdr = self .load_fw (f"psp_ { fmt_ver ( am . MP0_HWIP ) } _sos .bin" , am .struct_psp_firmware_header_v2_0 )
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fw_bin = sos_hdr .psp_fw_bin
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for fw_i in range (sos_hdr .psp_fw_bin_count ):
@@ -48,17 +50,17 @@ def __init__(self):
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self .ucode_start : dict [str , int ] = {}
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self .descs : list [tuple [int , memoryview ]] = []
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- blob , hdr = self .load_fw ("smu_13_0_0 .bin" , am .struct_smc_firmware_header_v1_0 )
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+ blob , hdr = self .load_fw (f"smu_ { fmt_ver ( am . MP1_HWIP ) } .bin" , am .struct_smc_firmware_header_v1_0 )
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self .smu_psp_desc = self .desc (am .GFX_FW_TYPE_SMU , blob , hdr .header .ucode_array_offset_bytes , hdr .header .ucode_size_bytes )
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# SDMA firmware
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- blob , hdr = self .load_fw ("sdma_6_0_0 .bin" , am .struct_sdma_firmware_header_v2_0 )
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+ blob , hdr = self .load_fw (f"sdma_ { fmt_ver ( am . SDMA0_HWIP ) } .bin" , am .struct_sdma_firmware_header_v2_0 )
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self .descs += [self .desc (am .GFX_FW_TYPE_SDMA_UCODE_TH0 , blob , hdr .header .ucode_array_offset_bytes , hdr .ctx_ucode_size_bytes )]
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self .descs += [self .desc (am .GFX_FW_TYPE_SDMA_UCODE_TH1 , blob , hdr .ctl_ucode_offset , hdr .ctl_ucode_size_bytes )]
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# PFP, ME, MEC firmware
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for (fw_name , fw_cnt ) in [('PFP' , 2 ), ('ME' , 2 ), ('MEC' , 4 )]:
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- blob , hdr = self .load_fw (f"gc_11_0_0_ { fw_name .lower ()} .bin" , am .struct_gfx_firmware_header_v2_0 )
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+ blob , hdr = self .load_fw (f"gc_ { fmt_ver ( am . GC_HWIP ) } _ { fw_name .lower ()} .bin" , am .struct_gfx_firmware_header_v2_0 )
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# Code part
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self .descs += [self .desc (getattr (am , f'GFX_FW_TYPE_RS64_{ fw_name } ' ), blob , hdr .header .ucode_array_offset_bytes , hdr .ucode_size_bytes )]
@@ -69,12 +71,12 @@ def __init__(self):
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self .ucode_start [fw_name ] = hdr .ucode_start_addr_lo | (hdr .ucode_start_addr_hi << 32 )
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# IMU firmware
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- blob , hdr = self .load_fw ("gc_11_0_0_imu .bin" , am .struct_imu_firmware_header_v1_0 )
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+ blob , hdr = self .load_fw (f"gc_ { fmt_ver ( am . GC_HWIP ) } _imu .bin" , am .struct_imu_firmware_header_v1_0 )
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imu_i_off , imu_i_sz , imu_d_sz = hdr .header .ucode_array_offset_bytes , hdr .imu_iram_ucode_size_bytes , hdr .imu_dram_ucode_size_bytes
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self .descs += [self .desc (am .GFX_FW_TYPE_IMU_I , blob , imu_i_off , imu_i_sz ), self .desc (am .GFX_FW_TYPE_IMU_D , blob , imu_i_off + imu_i_sz , imu_d_sz )]
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# RLC firmware
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- blob , hdr0 , hdr1 , hdr2 , hdr3 = self .load_fw ("gc_11_0_0_rlc .bin" , am .struct_rlc_firmware_header_v2_0 ,
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+ blob , hdr0 , hdr1 , hdr2 , hdr3 = self .load_fw (f"gc_ { fmt_ver ( am . GC_HWIP ) } _rlc .bin" , am .struct_rlc_firmware_header_v2_0 ,
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am .struct_rlc_firmware_header_v2_1 , am .struct_rlc_firmware_header_v2_2 , am .struct_rlc_firmware_header_v2_3 )
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for mem in ['GPM' , 'SRM' ]:
@@ -263,7 +265,7 @@ def __init__(self, devfmt, vram_bar:memoryview, doorbell_bar:memoryview, mmio_ba
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# Memory manager & firmware
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self .mm = AMMemoryManager (self , self .vram_size )
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- self .fw = AMFirmware ()
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+ self .fw = AMFirmware (self )
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# Initialize IP blocks
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self .soc21 :AM_SOC21 = AM_SOC21 (self )
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