-
Notifications
You must be signed in to change notification settings - Fork 12
/
Copy pathwb_conmax_arb.vhd
238 lines (220 loc) · 7.61 KB
/
wb_conmax_arb.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_arb.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2011-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Simple arbiter with round robin. It does not use any prioritization for
-- WB Masters.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_conmax_arb is
port(
clk_i : in std_logic;
rst_i : in std_logic;
--req_i(n) <- wb_cyc from n-th Master
req_i : in std_logic_vector(7 downto 0);
next_i : in std_logic;
--which master (0 to 7) is granted
gnt_o : out std_logic_vector(2 downto 0)
);
end wb_conmax_arb;
architecture behaviour of wb_conmax_arb is
type t_arb_states is (GRANT0, GRANT1, GRANT2, GRANT3, GRANT4, GRANT5,
GRANT6, GRANT7);
signal s_state : t_arb_states;
begin
--state transitions
process(clk_i)
begin
if(clk_i'event and clk_i='1') then
if(rst_i = '1') then
s_state <= GRANT0;
else
case s_state is
when GRANT0 =>
--if this req is dropped or next is asserted, check for other req's
if(req_i(0)='0' or next_i='1') then
if ( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
end if;
end if;
when GRANT1 =>
if(req_i(1)='0' or next_i='1') then
if ( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
end if;
end if;
when GRANT2 =>
if(req_i(2)='0' or next_i='1') then
if ( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
end if;
end if;
when GRANT3 =>
if(req_i(3)='0' or next_i='1') then
if ( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
end if;
end if;
when GRANT4 =>
if(req_i(4)='0' or next_i='1') then
if ( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
end if;
end if;
when GRANT5 =>
if(req_i(5)='0' or next_i='1') then
if ( req_i(6)='1' ) then
s_state <= GRANT6;
elsif( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
end if;
end if;
when GRANT6 =>
if(req_i(6)='0' or next_i='1') then
if ( req_i(7)='1' ) then
s_state <= GRANT7;
elsif( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
end if;
end if;
when GRANT7 =>
if(req_i(7)='0' or next_i='1') then
if ( req_i(0)='1' ) then
s_state <= GRANT0;
elsif( req_i(1)='1' ) then
s_state <= GRANT1;
elsif( req_i(2)='1' ) then
s_state <= GRANT2;
elsif( req_i(3)='1' ) then
s_state <= GRANT3;
elsif( req_i(4)='1' ) then
s_state <= GRANT4;
elsif( req_i(5)='1' ) then
s_state <= GRANT5;
elsif( req_i(6)='1' ) then
s_state <= GRANT6;
end if;
end if;
when others =>
s_state <= GRANT0;
end case;
end if;
end if;
end process;
process(s_state)
begin
case(s_state) is
when GRANT0 => gnt_o <= "000";
when GRANT1 => gnt_o <= "001";
when GRANT2 => gnt_o <= "010";
when GRANT3 => gnt_o <= "011";
when GRANT4 => gnt_o <= "100";
when GRANT5 => gnt_o <= "101";
when GRANT6 => gnt_o <= "110";
when GRANT7 => gnt_o <= "111";
when others => gnt_o <= "000";
end case;
end process;
end behaviour;