From 5b521c39f888cfb134e49e7e852e0c6c37f7a2cc Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Mon, 24 Jun 2024 09:59:59 -0300 Subject: [PATCH] Replace the FMC250/130 I2C Si57x master interface with xwb_si57x_ctrl The xwb_si57x_ctrl core provides an higher level interface for Si57x programmable oscillators, the software side doesn't need to control a RAW I2C interface anymore. --- modules/wishbone/ifc_wishbone_pkg.vhd | 6 ++ .../wb_fmc130m_4ch/wb_fmc130m_4ch.vhd | 4 ++ .../wb_fmc250m_4ch/wb_fmc250m_4ch.vhd | 4 ++ .../wb_fmc_active_clk/wb_fmc_active_clk.vhd | 67 ++++++++++--------- .../wb_fmc_active_clk/xwb_fmc_active_clk.vhd | 6 ++ 5 files changed, 56 insertions(+), 31 deletions(-) diff --git a/modules/wishbone/ifc_wishbone_pkg.vhd b/modules/wishbone/ifc_wishbone_pkg.vhd index 0a7c1ff..f0b3020 100644 --- a/modules/wishbone/ifc_wishbone_pkg.vhd +++ b/modules/wishbone/ifc_wishbone_pkg.vhd @@ -2201,6 +2201,9 @@ package ifc_wishbone_pkg is component wb_fmc_active_clk generic ( + g_si57x_i2c_addr : std_logic_vector(6 downto 0); + g_si57x_7ppm_variant : boolean; + g_si57x_i2c_clk_div : natural range 1 to 65536; g_interface_mode : t_wishbone_interface_mode := CLASSIC; g_address_granularity : t_wishbone_address_granularity := WORD; g_with_extra_wb_reg : boolean := false @@ -2267,6 +2270,9 @@ package ifc_wishbone_pkg is component xwb_fmc_active_clk generic ( + g_si57x_i2c_addr : std_logic_vector(6 downto 0); + g_si57x_7ppm_variant : boolean; + g_si57x_i2c_clk_div : natural range 1 to 65536; g_interface_mode : t_wishbone_interface_mode := CLASSIC; g_address_granularity : t_wishbone_address_granularity := WORD; g_with_extra_wb_reg : boolean := false diff --git a/modules/wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd b/modules/wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd index 0e973d1..c8a5e5b 100755 --- a/modules/wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd +++ b/modules/wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd @@ -1169,6 +1169,10 @@ begin -- FMC Active Clock is slave number 2, word addressed cmp_fmc_active_clk : xwb_fmc_active_clk generic map( + -- I2C address for Si571AJC000337DG + g_si57x_i2c_addr => "1001001", + g_si57x_7ppm_variant => false, + g_si57x_i2c_clk_div => 1000, g_interface_mode => g_interface_mode, g_address_granularity => g_address_granularity, g_with_extra_wb_reg => g_with_extra_wb_reg diff --git a/modules/wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd b/modules/wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd index 7940b1f..fb55355 100644 --- a/modules/wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd +++ b/modules/wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd @@ -1235,6 +1235,10 @@ begin cmp_fmc_active_clk : xwb_fmc_active_clk generic map( + -- I2C address for Si571AJC000337DG + g_si57x_i2c_addr => "1001001", + g_si57x_7ppm_variant => false, + g_si57x_i2c_clk_div => 1000, g_interface_mode => g_interface_mode, g_address_granularity => g_address_granularity, g_with_extra_wb_reg => g_with_extra_wb_reg diff --git a/modules/wishbone/wb_fmc_active_clk/wb_fmc_active_clk.vhd b/modules/wishbone/wb_fmc_active_clk/wb_fmc_active_clk.vhd index 9625e4f..bab9c1c 100644 --- a/modules/wishbone/wb_fmc_active_clk/wb_fmc_active_clk.vhd +++ b/modules/wishbone/wb_fmc_active_clk/wb_fmc_active_clk.vhd @@ -31,6 +31,9 @@ use work.wb_fmc_active_clk_csr_wbgen2_pkg.all; entity wb_fmc_active_clk is generic ( + g_si57x_i2c_addr : std_logic_vector(6 downto 0); + g_si57x_7ppm_variant : boolean; + g_si57x_i2c_clk_div : natural range 1 to 65536; g_interface_mode : t_wishbone_interface_mode := CLASSIC; g_address_granularity : t_wishbone_address_granularity := WORD; g_with_extra_wb_reg : boolean := false @@ -115,7 +118,7 @@ architecture rtl of wb_fmc_active_clk is constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := ( 0 => f_sdb_embed_device(c_xwb_fmc_active_clk_regs_sdb, x"00000000"), -- FMC Active Clock Interface regs - 1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00000100"), -- VCXO Si571 I2C + 1 => f_sdb_embed_device(c_xwb_si57x_ctrl_regs_sdb, x"00000100"), -- VCXO Si571 controller 2 => f_sdb_embed_device(c_xwb_spi_sdb, x"00000200") -- AD9510 SPI ); @@ -163,12 +166,12 @@ architecture rtl of wb_fmc_active_clk is ----------------------------- -- VCXO Si571 I2C Signals ----------------------------- - signal si571_i2c_scl_in : std_logic_vector(0 downto 0); - signal si571_i2c_scl_out : std_logic_vector(0 downto 0); - signal si571_i2c_scl_oe_n : std_logic_vector(0 downto 0); - signal si571_i2c_sda_in : std_logic_vector(0 downto 0); - signal si571_i2c_sda_out : std_logic_vector(0 downto 0); - signal si571_i2c_sda_oe_n : std_logic_vector(0 downto 0); + signal si571_i2c_scl_in : std_logic; + signal si571_i2c_scl_out : std_logic; + signal si571_i2c_scl_oe : std_logic; + signal si571_i2c_sda_in : std_logic; + signal si571_i2c_sda_out : std_logic; + signal si571_i2c_sda_oe : std_logic; ----------------------------- -- Components @@ -364,32 +367,34 @@ begin -- I2C Programmable VCXO is slave number 1, word addressed -- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers - cmp_vcxo_i2c : xwb_i2c_master - generic map( - g_interface_mode => g_interface_mode, - g_address_granularity => g_address_granularity - ) - port map ( - clk_sys_i => sys_clk_i, - rst_n_i => sys_rst_n_i, - - slave_i => cbar_master_out(1), - slave_o => cbar_master_in(1), - desc_o => open, - - scl_pad_i => si571_i2c_scl_in, - scl_pad_o => si571_i2c_scl_out, - scl_padoen_o => si571_i2c_scl_oe_n, - sda_pad_i => si571_i2c_sda_in, - sda_pad_o => si571_i2c_sda_out, - sda_padoen_o => si571_i2c_sda_oe_n - ); + cmp_xwb_si57x_ctrl: xwb_si57x_ctrl + generic map ( + g_si57x_i2c_addr => g_si57x_i2c_addr, + g_scl_clk_div => g_si57x_i2c_clk_div, + g_si57x_7ppm_variant => g_si57x_7ppm_variant, + g_interface_mode => g_interface_mode, + g_address_granularity => g_address_granularity + ) + port map ( + clk_i => sys_clk_i, + rst_n_i => sys_rst_n_i, + + wb_slv_i => cbar_master_out(1), + wb_slv_o => cbar_master_in(1), + + sda_i => si571_i2c_sda_in, + sda_o => si571_i2c_sda_out, + sda_oe_o => si571_i2c_sda_oe, + scl_i => si571_i2c_scl_in, + scl_o => si571_i2c_scl_out, + scl_oe_o => si571_i2c_scl_oe + ); - si571_scl_pad_b <= si571_i2c_scl_out(0) when si571_i2c_scl_oe_n(0) = '0' else 'Z'; - si571_i2c_scl_in(0) <= si571_scl_pad_b; + si571_scl_pad_b <= si571_i2c_scl_out when si571_i2c_scl_oe = '1' else 'Z'; + si571_i2c_scl_in <= si571_scl_pad_b; - si571_sda_pad_b <= si571_i2c_sda_out(0) when si571_i2c_sda_oe_n(0) = '0' else 'Z'; - si571_i2c_sda_in(0) <= si571_sda_pad_b; + si571_sda_pad_b <= si571_i2c_sda_out when si571_i2c_sda_oe = '1' else 'Z'; + si571_i2c_sda_in <= si571_sda_pad_b; -- Not used wishbone signals --cbar_master_in(1).err <= '0'; diff --git a/modules/wishbone/wb_fmc_active_clk/xwb_fmc_active_clk.vhd b/modules/wishbone/wb_fmc_active_clk/xwb_fmc_active_clk.vhd index 0b8e17e..1a5b352 100644 --- a/modules/wishbone/wb_fmc_active_clk/xwb_fmc_active_clk.vhd +++ b/modules/wishbone/wb_fmc_active_clk/xwb_fmc_active_clk.vhd @@ -29,6 +29,9 @@ use work.ifc_wishbone_pkg.all; entity xwb_fmc_active_clk is generic ( + g_si57x_i2c_addr : std_logic_vector(6 downto 0); + g_si57x_7ppm_variant : boolean; + g_si57x_i2c_clk_div : natural range 1 to 65536; g_interface_mode : t_wishbone_interface_mode := CLASSIC; g_address_granularity : t_wishbone_address_granularity := WORD; g_with_extra_wb_reg : boolean := false @@ -89,6 +92,9 @@ begin cmp_wb_fmc_active_clk : wb_fmc_active_clk generic map ( + g_si57x_i2c_addr => g_si57x_i2c_addr, + g_si57x_7ppm_variant => g_si57x_7ppm_variant, + g_si57x_i2c_clk_div => g_si57x_i2c_clk_div, g_interface_mode => g_interface_mode, g_address_granularity => g_address_granularity, g_with_extra_wb_reg => g_with_extra_wb_reg