@@ -160,12 +160,12 @@ REG32(MAIN_SM_STATE, 0x5cu)
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(R_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK | \
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R_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_MASK | \
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R_RECOV_ALERT_STS_READ_INT_STATE_FIELD_ALERT_MASK | \
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- R_RECOV_ALERT_STS_FIPS_FORCE_ENABLE_FIELD_ALERT | \
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- R_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT | \
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+ R_RECOV_ALERT_STS_FIPS_FORCE_ENABLE_FIELD_ALERT_MASK | \
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+ R_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT_MASK | \
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R_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_MASK | \
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- R_RECOV_ALERT_STS_CMD_STAGE_INVALID_ACMD_ALERT | \
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- R_RECOV_ALERT_STS_CMD_STAGE_INVALID_CMD_SEQ_ALERT | \
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- R_RECOV_ALERT_STS_CMD_STAGE_RESEED_CNT_ALERT )
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+ R_RECOV_ALERT_STS_CMD_STAGE_INVALID_ACMD_ALERT_MASK | \
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+ R_RECOV_ALERT_STS_CMD_STAGE_INVALID_CMD_SEQ_ALERT_MASK | \
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+ R_RECOV_ALERT_STS_CMD_STAGE_INVALID_RESEED_CNT_ALERT_MASK )
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#define ERR_CODE_MASK 0x77e0ffffu
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#define OT_CSRNG_AES_KEY_SIZE 32u /* 256 bits */
@@ -885,7 +885,7 @@ static void ot_csrng_update_alerts(OtCSRNGState *s)
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uint32_t level = s -> regs [R_ALERT_TEST ];
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s -> regs [R_ALERT_TEST ] = 0u ;
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- if (__builtin_popcount ( s -> regs [R_RECOV_ALERT_STS ]) ) {
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+ if (s -> regs [R_RECOV_ALERT_STS ]) {
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level |= 1u << ALERT_RECOVERABLE ;
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}
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@@ -1945,6 +1945,15 @@ static void ot_csrng_regs_write(void *opaque, hwaddr addr, uint64_t val64,
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val32 &= R_FIPS_FORCE_VAL_MASK ;
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s -> regs [reg ] = val32 ;
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break ;
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+ case R_HW_EXC_STS :
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+ val32 &= R_HW_EXC_STS_VAL_MASK ;
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+ s -> regs [reg ] &= val32 ; /* RW0C */
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+ break ;
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+ case R_RECOV_ALERT_STS :
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+ val32 &= RECOV_ALERT_STS_MASK ;
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+ s -> regs [reg ] &= val32 ; /* RW0C */
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+ ot_csrng_update_alerts (s );
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+ break ;
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case R_ERR_CODE_TEST :
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if (!s -> regs [R_REGWEN ]) {
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qemu_log_mask (LOG_GUEST_ERROR , "%s: %s protected w/ REGWEN\n" ,
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