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rivos-eblotloiclefort
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[ot] hw/riscv: ot_darjeeling, ot_earlgrey: connect PWRMGR reset request line to RSTMGR
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
1 parent 63b2c3b commit 5777b97

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2 files changed

+8
-10
lines changed

2 files changed

+8
-10
lines changed

hw/riscv/ot_darjeeling.c

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1230,10 +1230,9 @@ static const IbexDeviceDef ot_dj_soc_devices[] = {
12301230
OT_DJ_SOC_SIGNAL(OT_PWRMGR_CPU_EN, 0, IBEX_WRAPPER,
12311231
OT_IBEX_WRAPPER_CPU_EN, OT_IBEX_PWRMGR_CPU_EN),
12321232
OT_DJ_SOC_SIGNAL(OT_PWRMGR_STRAP, 0, GPIO,
1233-
OT_GPIO_STRAP_EN, 0)
1234-
),
1235-
.link = IBEXDEVICELINKDEFS(
1236-
OT_DJ_SOC_DEVLINK("rstmgr", RSTMGR)
1233+
OT_GPIO_STRAP_EN, 0),
1234+
OT_DJ_SOC_SIGNAL(OT_PWRMGR_RST_REQ, 0, RSTMGR,
1235+
OT_RSTMGR_RST_REQ, 0)
12371236
),
12381237
.prop = IBEXDEVICEPROPDEFS(
12391238
IBEX_DEV_UINT_PROP("num-rom", 2u),

hw/riscv/ot_earlgrey.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -639,19 +639,18 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
639639
OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 152),
640640
/* loopback signal since Earlgrey OTP signal are not supported yet*/
641641
OT_EG_SOC_SIGNAL(OT_PWRMGR_OTP_REQ, 0, PWRMGR,
642-
OT_PWRMGR_OTP_RSP, 0),
642+
OT_PWRMGR_OTP_RSP, 0),
643643
OT_EG_SOC_REQ(OT_PWRMGR_LC, LC_CTRL),
644644
OT_EG_SOC_SIGNAL(OT_PWRMGR_CPU_EN, 0, IBEX_WRAPPER,
645-
OT_IBEX_WRAPPER_CPU_EN,
646-
OT_IBEX_PWRMGR_CPU_EN)
645+
OT_IBEX_WRAPPER_CPU_EN,
646+
OT_IBEX_PWRMGR_CPU_EN),
647+
OT_EG_SOC_SIGNAL(OT_PWRMGR_RST_REQ, 0, RSTMGR,
648+
OT_RSTMGR_RST_REQ, 0)
647649
),
648650
.prop = IBEXDEVICEPROPDEFS(
649651
IBEX_DEV_UINT_PROP("num-rom", 1u),
650652
IBEX_DEV_UINT_PROP("version", OT_PWMGR_VERSION_EG)
651653
),
652-
.link = IBEXDEVICELINKDEFS(
653-
OT_EG_SOC_DEVLINK("rstmgr", RSTMGR)
654-
),
655654
},
656655
[OT_EG_SOC_DEV_RSTMGR] = {
657656
.type = TYPE_OT_RSTMGR,

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