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1 | 1 | /*
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2 | 2 | * QEMU OpenTitan SPI Device controller
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3 | 3 | *
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4 |
| - * Copyright (c) 2023-2024 Rivos, Inc. |
| 4 | + * Copyright (c) 2023-2025 Rivos, Inc. |
5 | 5 | *
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6 | 6 | * Author(s):
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7 | 7 | * Emmanuel Blot <eblot@rivosinc.com>
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@@ -364,25 +364,10 @@ typedef enum {
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364 | 364 | READ_QUAD,
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365 | 365 | READ_DUAL_IO,
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366 | 366 | READ_QUAD_IO,
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| 367 | + HW_COMMAND_COUNT |
367 | 368 | } SpiDeviceHwCommand;
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368 | 369 |
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369 |
| -static const uint8_t SPI_DEVICE_HW_COMMANDS[] = { |
370 |
| - /* clang-format off */ |
371 |
| - [READ_STATUS1] = 0x05u, |
372 |
| - [READ_STATUS2] = 0x35u, |
373 |
| - [READ_STATUS3] = 0x15u, |
374 |
| - [READ_JEDEC] = 0x9fu, |
375 |
| - [READ_SFDP] = 0x5au, |
376 |
| - [READ_NORMAL] = 0x03u, |
377 |
| - [READ_FAST] = 0x0bu, |
378 |
| - [READ_DUAL] = 0x3bu, |
379 |
| - [READ_QUAD] = 0x6bu, |
380 |
| - [READ_DUAL_IO] = 0xbbu, |
381 |
| - [READ_QUAD_IO] = 0xebu, |
382 |
| - /* clang-format on */ |
383 |
| -}; |
384 |
| - |
385 |
| -#define SPI_DEVICE_CMD_HW_STA_COUNT ARRAY_SIZE(SPI_DEVICE_HW_COMMANDS) |
| 370 | +#define SPI_DEVICE_CMD_HW_STA_COUNT ((unsigned)HW_COMMAND_COUNT) |
386 | 371 | #define SPI_DEVICE_CMD_HW_STA_FIRST 0
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387 | 372 | #define SPI_DEVICE_CMD_HW_STA_LAST (SPI_DEVICE_CMD_HW_STA_COUNT - 1u)
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388 | 373 | #define SPI_DEVICE_CMD_HW_CFG_FIRST (R_CMD_INFO_EN4B - R_CMD_INFO_0)
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@@ -1123,34 +1108,24 @@ static void ot_spi_device_flash_decode_command(OtSPIDeviceState *s, uint8_t cmd)
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1123 | 1108 | {
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1124 | 1109 | SpiDeviceFlash *f = &s->flash;
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1125 | 1110 |
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1126 |
| - /* search command slot in HW-handling commands (static group) */ |
1127 | 1111 | if (f->state == SPI_FLASH_IDLE) {
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1128 |
| - for (unsigned ix = 0; ix < SPI_DEVICE_CMD_HW_STA_COUNT; ix++) { |
1129 |
| - if (cmd == SPI_DEVICE_HW_COMMANDS[ix]) { |
1130 |
| - f->type = SPI_FLASH_CMD_HW_STA; |
1131 |
| - f->slot = ix; |
1132 |
| - f->cmd_info = SHARED_FIELD_DP32(s->spi_regs[R_CMD_INFO_0 + ix], |
1133 |
| - CMD_INFO_OPCODE, cmd); |
1134 |
| - trace_ot_spi_device_flash_new_command("HW", cmd, f->slot); |
1135 |
| - break; |
1136 |
| - } |
1137 |
| - } |
1138 |
| - } |
1139 |
| - |
1140 |
| - /* search command in other slots */ |
1141 |
| - if (f->state == SPI_FLASH_IDLE) { |
1142 |
| - for (unsigned ix = SPI_DEVICE_CMD_HW_STA_COUNT; |
| 1112 | + for (unsigned ix = 0; |
1143 | 1113 | ix < PARAM_NUM_CMD_INFO + SPI_DEVICE_CMD_HW_CFG_COUNT; ix++) {
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1144 | 1114 | uint32_t val32 = s->spi_regs[R_CMD_INFO_0 + ix];
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1145 |
| - if (cmd == SHARED_FIELD_EX32(val32, CMD_INFO_OPCODE)) { |
| 1115 | + if (cmd == (uint8_t)SHARED_FIELD_EX32(val32, CMD_INFO_OPCODE)) { |
1146 | 1116 | if (SHARED_FIELD_EX32(val32, CMD_INFO_VALID)) {
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1147 |
| - f->type = ix < PARAM_NUM_CMD_INFO ? SPI_FLASH_CMD_SW : |
1148 |
| - SPI_FLASH_CMD_HW_CFG; |
| 1117 | + f->type = |
| 1118 | + ix < SPI_DEVICE_CMD_HW_STA_COUNT ? |
| 1119 | + SPI_FLASH_CMD_HW_STA : |
| 1120 | + (ix < PARAM_NUM_CMD_INFO ? SPI_FLASH_CMD_SW : |
| 1121 | + SPI_FLASH_CMD_HW_CFG); |
1149 | 1122 | f->slot = ix;
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1150 | 1123 | f->cmd_info = val32;
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1151 | 1124 | trace_ot_spi_device_flash_new_command(
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1152 |
| - f->type == SPI_FLASH_CMD_SW ? "SW" : "HW_CFG", cmd, |
1153 |
| - f->slot); |
| 1125 | + f->type == SPI_FLASH_CMD_HW_STA ? |
| 1126 | + "HW" : |
| 1127 | + (f->type == SPI_FLASH_CMD_SW ? "SW" : "HW_CFG"), |
| 1128 | + cmd, f->slot); |
1154 | 1129 | break;
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1155 | 1130 | }
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1156 | 1131 | trace_ot_spi_device_flash_disabled_slot(cmd, ix);
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@@ -1285,24 +1260,24 @@ static void ot_spi_device_flash_decode_hw_static_command(OtSPIDeviceState *s)
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1285 | 1260 | {
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1286 | 1261 | SpiDeviceFlash *f = &s->flash;
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1287 | 1262 |
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1288 |
| - switch (COMMAND_OPCODE(f->cmd_info)) { |
1289 |
| - case 0x05u: /* READ_STATUS_1 */ |
1290 |
| - case 0x35u: /* READ_STATUS_2 */ |
1291 |
| - case 0x15u: /* READ_STATUS_3 */ |
| 1263 | + switch ((int)f->slot) { |
| 1264 | + case READ_STATUS1: |
| 1265 | + case READ_STATUS2: |
| 1266 | + case READ_STATUS3: |
1292 | 1267 | ot_spi_device_flash_decode_read_status(s);
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1293 | 1268 | break;
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1294 |
| - case 0x9fu: /* READ_JEDEC */ |
| 1269 | + case READ_JEDEC: |
1295 | 1270 | ot_spi_device_flash_decode_read_jedec(s);
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1296 | 1271 | break;
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1297 |
| - case 0x5au: /* READ_SFDP */ |
| 1272 | + case READ_SFDP: |
1298 | 1273 | ot_spi_device_flash_decode_read_sfdp(s);
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1299 | 1274 | break;
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1300 |
| - case 0x03u: /* READ_NORMAL */ |
1301 |
| - case 0x0bu: /* READ_FAST */ |
1302 |
| - case 0x3bu: /* READ_DUAL */ |
1303 |
| - case 0x6bu: /* READ_QUAD */ |
1304 |
| - case 0xbbu: /* READ_DUALIO */ |
1305 |
| - case 0xebu: /* READ_QUADIO */ |
| 1275 | + case READ_NORMAL: |
| 1276 | + case READ_FAST: |
| 1277 | + case READ_DUAL: |
| 1278 | + case READ_QUAD: |
| 1279 | + case READ_DUAL_IO: |
| 1280 | + case READ_QUAD_IO: |
1306 | 1281 | ot_spi_device_flash_decode_read_data(s);
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1307 | 1282 | break;
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1308 | 1283 | default:
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