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8ba0172
[ot] hw/opentitan: ot_fifo32: update function signatures with const
rivos-eblot Mar 18, 2025
11a61f1
[ot] hw/opentitan: ot_common: make ot_common_configure_device_opts pu…
rivos-eblot Mar 25, 2025
0aaf0fe
[ot] hw/riscv: ot_earlgrey: remove invalid EDN reference from LC_CTRL
rivos-eblot Mar 18, 2025
59e0a6a
[ot] hw/riscv: ot_earlgrey: warn only once on dummy devices access
rivos-eblot Mar 21, 2025
8a55b0c
[ot] hw/riscv: ot_earlgrey: add a Verilator-compliant clock mode
rivos-eblot Mar 25, 2025
2a00cb1
[ot] hw/opentitan: ot_entropy_src: fix timing hint computation.
rivos-eblot Mar 18, 2025
523fe74
[ot] hw/opentitan: ot_entropy_src: update register definitions
rivos-eblot Mar 21, 2025
1815a69
[ot] hw/opentitan: ot_csrng: rework CSRNG to match new implementation
rivos-eblot Mar 6, 2025
47a1a1b
[ot] hw/opentitan: ot_edn: rework EDN to match new HW implementation
rivos-eblot Mar 6, 2025
82b2434
[ot] hw/opentitan: ot_aes: add trace for selected reseed rates
rivos-eblot Mar 25, 2025
9ce285a
[ot] hw/opentitan: ot_aes: delay status_output_valid bit
rivos-eblot Mar 26, 2025
5db08f1
[ot] hw/opentitan: ot_csrng: rework FIPS compliance tracking
rivos-eblot Mar 26, 2025
ea472b7
[ot] hw/opentitan: ot_edn: rework FIPS compliance tracking
rivos-eblot Mar 27, 2025
607104c
[ot] hw/opentitan: ot_otbn: reformat code
rivos-eblot Mar 27, 2025
8ded7d9
[ot] hw/opentitan: ot_otbn: enable reporting errors without tracing e…
rivos-eblot Mar 26, 2025
14da388
[ot] python/qemu: ot.pyot.executer: fix a bug when a single ROM is used.
rivos-eblot Mar 27, 2025
1252a03
[ot] hw/riscv: ot_darjeeling: remove OT_SENSOR
rivos-eblot Mar 27, 2025
2bb9303
[ot] hw/opentitan: ot_sensor: renamed as ot_sensor_eg
rivos-eblot Mar 27, 2025
c18ae56
[ot] hw/opentitan: ot_sensor_eg: update register definitions
rivos-eblot Mar 27, 2025
e0f018b
[ot] hw/opentitan: ot_entropy_src: improve trace messages
rivos-eblot Mar 26, 2025
6f13500
[ot] hw/opentitan: ot_edn: add a sanity check on command sequence.
rivos-eblot Mar 27, 2025
72539c0
[ot] hw/opentitan: ot_edn: fix issues with disablement handling.
rivos-eblot Mar 27, 2025
cc9852e
[ot] hw/opentitan: ot_edn: replace legacy reset with Resettable imple…
rivos-eblot Mar 27, 2025
051db71
[ot] hw/opentitan: ot_common: redefine some OBJECT macro with an expl…
rivos-eblot Mar 27, 2025
b66b17a
[ot] hw/opentitan: ot_ibex_wrapper: rename OtIbexWrapperStateClass
rivos-eblot Mar 27, 2025
87dfad7
[ot] hw/opentitan: ot_ibex_wrapper: replace legacy reset with Resetta…
rivos-eblot Mar 27, 2025
846e6f1
[ot] hw/opentitan: ot_ibex_wrapper: add reset_exit implementation
rivos-eblot Mar 27, 2025
ee3bf12
[ot] hw/opentitan: ot_csrng: fix connection management
rivos-eblot Mar 27, 2025
5c06e48
[ot] hw/opentitan: ot_edn: delayed mode change is legit, not an error
rivos-eblot Mar 27, 2025
56f0be5
[ot] hw/opentitan: ot_csrng: add missing write access to 2 new registers
rivos-eblot Mar 27, 2025
3fca6e4
[ot] hw/opentitan: ot_entropy_src: add missing read access to 1 register
rivos-eblot Mar 27, 2025
cba42e2
[ot] python/qemu: ot.eflash.gen: fix a bug when storing an ELF file
rivos-eblot Mar 28, 2025
4b69ff8
[ot] hw/opentitan: ot_entropy_src: ignore generation identifier
rivos-eblot Mar 28, 2025
106fc51
[ot] hw/opentitan: ot_entropy_src: fix initial values
rivos-eblot Mar 28, 2025
b9a909b
[ot] hw/opentitan: ot_otbn: fix FIPS compliance management
rivos-eblot Mar 28, 2025
9d8ad42
[ot] hw/opentitan: ot_random_src: rework interface and implementation
rivos-eblot Mar 31, 2025
3838be9
[ot] .gitlab-ci.d: opentitan: update BM tests
rivos-eblot Mar 18, 2025
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2 changes: 1 addition & 1 deletion .gitlab-ci.d/opentitan/qemu-ot.yml
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
variables:
BAREMETAL_REF: "b0-250310-1"
BAREMETAL_REF: "b0-250325-1"
QEMU_BUILD_OPTS: "--disable-install-blobs"

include:
Expand Down
11 changes: 9 additions & 2 deletions docs/opentitan/earlgrey.md
Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,9 @@ See [`tools.md`](tools.md)
update the vCPU reset vector at startup. When this option is used, with `-kernel` option for
example, the application is loaded in memory but the default machine reset vector is used.

* `verilator=true` can be appended to the machine option switch, to select Verilator lowered clocks:
_i.e._ `-M ot-earlgrey,verilator=true` to select Verilator reduced clock rates.

* `-cpu lowrisc-ibex,x-zbr=false` can be used to force disable the Zbr experimental-and-deprecated
RISC-V bitmap extension for CRC32 extension.

Expand Down Expand Up @@ -155,8 +158,12 @@ See [`tools.md`](tools.md)

### OTBN

* `-global ot-otbn.logfile=<filename>` dumps executed instructions on OTBN core into the specified
filename. Beware that is even further slows down execution speed, which could likely result into
* `-global ot-otbn.logfile=<filename>` output OTBN execution message to the specified logfile. When
_logasm_ option (see below) is not enabled, only execution termination and error messages are
logged. `stderr` can be used to log the messages to the standard error stream instead of a file.

* `-global ot-otbn.logasm=<true|false>` dumps executed instructions on OTBN core into the _logfile_
filename. Beware that this further slows down execution speed, which could likely result in the
guest application on the Ibex core to time out.

### OTP
Expand Down
2 changes: 1 addition & 1 deletion hw/opentitan/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -138,7 +138,7 @@ config OT_ROM_CTRL
config OT_RSTMGR
bool

config OT_SENSOR
config OT_SENSOR_EG
bool

config OT_SOC_PROXY
Expand Down
2 changes: 1 addition & 1 deletion hw/opentitan/meson.build
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ system_ss.add(when: 'CONFIG_OT_PWRMGR', if_true: files('ot_pwrmgr.c'))
system_ss.add(when: 'CONFIG_OT_RANDOM_SRC', if_true: files('ot_random_src.c'))
system_ss.add(when: 'CONFIG_OT_ROM_CTRL', if_true: files('ot_rom_ctrl.c', 'ot_rom_ctrl_img.c'))
system_ss.add(when: 'CONFIG_OT_RSTMGR', if_true: files('ot_rstmgr.c'))
system_ss.add(when: 'CONFIG_OT_SENSOR', if_true: files('ot_sensor.c'))
system_ss.add(when: 'CONFIG_OT_SENSOR_EG', if_true: files('ot_sensor_eg.c'))
system_ss.add(when: 'CONFIG_OT_SOC_PROXY', if_true: files('ot_soc_proxy.c'))
system_ss.add(when: 'CONFIG_OT_SOCDBG_CTRL', if_true: files('ot_socdbg_ctrl.c'))
system_ss.add(when: 'CONFIG_OT_SPI_DEVICE', if_true: files('ot_spi_device.c'))
Expand Down
32 changes: 29 additions & 3 deletions hw/opentitan/ot_aes.c
Original file line number Diff line number Diff line change
Expand Up @@ -201,6 +201,7 @@ typedef struct OtAESRegisters {
DECLARE_BITMAP(data_in_bm, PARAM_NUM_REGS_DATA);
DECLARE_BITMAP(data_out_bm, PARAM_NUM_REGS_DATA);
uint32_t key[PARAM_NUM_REGS_KEY];
bool data_out_rdy; /* AES output data exist, not yet published */
} OtAESRegisters;

typedef struct OtAESContext {
Expand Down Expand Up @@ -399,6 +400,8 @@ static inline void ot_aes_load_reseed_rate(OtAESState *s)
break;
}

trace_ot_aes_reseed_rate(reseed);

s->reseed_count = reseed;
}

Expand Down Expand Up @@ -803,9 +806,7 @@ static void ot_aes_push(OtAESState *s)

memcpy(r->data_out, c->dst, sizeof(c->dst));
memcpy(r->iv, c->iv, sizeof(c->iv));
bitmap_fill(r->data_out_bm, PARAM_NUM_REGS_DATA);

r->status |= R_STATUS_OUTPUT_VALID_MASK;
r->data_out_rdy = true;
}

static void ot_aes_process(OtAESState *s)
Expand Down Expand Up @@ -898,6 +899,15 @@ static void ot_aes_process(OtAESState *s)
}
}

static void ot_aes_commit_data_out(OtAESRegisters *r)
{
if (r->data_out_rdy) {
bitmap_fill(r->data_out_bm, PARAM_NUM_REGS_DATA);
r->status |= R_STATUS_OUTPUT_VALID_MASK;
r->data_out_rdy = false;
}
}

static inline void ot_aes_do_process(OtAESState *s)
{
ot_aes_process(s);
Expand All @@ -906,10 +916,18 @@ static inline void ot_aes_do_process(OtAESState *s)
s->reseed_count -= 1u;
}
if (!s->reseed_count) {
/*
* delay availability of pushed data till completion of reseed
* otherwise, IDLE status may be false once the vCPU has read the data,
* which would not match the HW behavior
*/
trace_ot_aes_reseed("reseed_count reached");
s->regs->trigger |= R_TRIGGER_PRNG_RESEED_MASK;
ot_aes_trigger_reseed(s);
ot_aes_load_reseed_rate(s);
} else {
/* flag pushed data as immediately available */
ot_aes_commit_data_out(s->regs);
}

OtAESRegisters *r = s->regs;
Expand Down Expand Up @@ -968,6 +986,13 @@ static void ot_aes_fill_entropy(void *opaque, uint32_t bits, bool fips)
edn->scheduled = false;
r->trigger &= ~R_TRIGGER_PRNG_RESEED_MASK;

/*
* if a previous AES data output generation had completed, flag the output
* as valid, as this state was delayed till entropy collection was
* completed to maintain a coherent IDLE state.
*/
ot_aes_commit_data_out(r);

ot_prng_reseed(s->prng, bits);

ot_aes_handle_trigger(s);
Expand Down Expand Up @@ -1270,6 +1295,7 @@ static void ot_aes_reset(DeviceState *dev)
r->ctrl_aux_regwen = 1u;
r->trigger = 0xeu;
r->status = 0u;
r->data_out_rdy = false;
e->scheduled = false;
ot_aes_load_reseed_rate(s);

Expand Down
21 changes: 3 additions & 18 deletions hw/opentitan/ot_ast_dj.c
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
/*
* QEMU OpenTitan Darjeeling Analog Sensor Top device
*
* Copyright (c) 2023-2024 Rivos, Inc.
* Copyright (c) 2023-2025 Rivos, Inc.
*
* Author(s):
* Emmanuel Blot <eblot@rivosinc.com>
Expand Down Expand Up @@ -152,26 +152,12 @@ struct OtASTDjState {
/* Private implementation */
/* -------------------------------------------------------------------------- */

static int ot_ast_dj_get_generation(OtRandomSrcIf *dev)
{
(void)dev;

return -1;
}

static int ot_ast_dj_get_random(OtRandomSrcIf *dev, int genid,
uint64_t random[OT_RANDOM_SRC_DWORD_COUNT],
bool *fips)
static int ot_ast_dj_get_random(
OtRandomSrcIf *dev, uint64_t random[OT_RANDOM_SRC_DWORD_COUNT], bool *fips)
{
OtASTDjState *s = OT_AST_DJ(dev);
OtASTDjRandom *rnd = &s->random;

if (genid != -1) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: AST gennum mismatch req:%d\n",
__func__, genid);
return -2;
}

if (!rnd->avail) {
/* not ready */
trace_ot_ast_no_entropy(0);
Expand Down Expand Up @@ -441,7 +427,6 @@ static void ot_ast_dj_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_MISC, dc->categories);

OtRandomSrcIfClass *rdc = OT_RANDOM_SRC_IF_CLASS(klass);
rdc->get_random_generation = &ot_ast_dj_get_generation;
rdc->get_random_values = &ot_ast_dj_get_random;
}

Expand Down
6 changes: 3 additions & 3 deletions hw/opentitan/ot_common.c
Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
/*
* QEMU OpenTitan utilities
*
* Copyright (c) 2023 Rivos, Inc.
* Copyright (c) 2023-2024 Rivos, Inc.
* Copyright (c) 2025 lowRISC contributors.
*
* Author(s):
* Emmanuel Blot <eblot@rivosinc.com>
Expand Down Expand Up @@ -221,8 +222,7 @@ AddressSpace *ot_common_get_local_address_space(DeviceState *s)
return cpu ? cpu->as : NULL;
}

static void
ot_common_configure_device_opts(DeviceState **devices, unsigned count)
void ot_common_configure_device_opts(DeviceState **devices, unsigned count)
{
// TODO need to use qemu_find_opts_err if no config is ok
QemuOptsList *optlist = qemu_find_opts("ot_device");
Expand Down
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