diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py
index b2be757..44fc8fc 100644
--- a/nmigen_boards/resources/memory.py
+++ b/nmigen_boards/resources/memory.py
@@ -15,7 +15,10 @@ def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None,
     if attrs is not None:
         io_all.append(attrs)
     io_all.append(Subsignal("cs",  PinsN(cs, dir="o", conn=conn)))
-    io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
+    # Only append a Subsignal if no user clock is to be used as the SPI clock
+    # The user of user clock is indicated by `clk="user_clk"`
+    if clk is not None:
+        io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
 
     io_1x = list(io_all)
     io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", conn=conn, assert_width=1)))
diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py
index 4847d9a..350a1c2 100644
--- a/nmigen_boards/versa_ecp5.py
+++ b/nmigen_boards/versa_ecp5.py
@@ -6,16 +6,16 @@
 from .resources import *
 
 
-__all__ = ["VersaECP5Platform"]
+__all__ = ["VersaECP5Platform", "VersaECP5Platform_USRMCLK"]
 
 
-class VersaECP5Platform(LatticeECP5Platform):
+class _VersaECP5PlatformBase(LatticeECP5Platform):
     device      = "LFE5UM-45F"
     package     = "BG381"
     speed       = "8"
     default_clk = "clk100"
     default_rst = "rst"
-    resources   = [
+    _resources   = [
         Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
         Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
                  Clock(100e6), Attrs(IO_TYPE="LVDS")),
@@ -54,11 +54,6 @@ class VersaECP5Platform(LatticeECP5Platform):
             attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
         ),
 
-        *SPIFlashResources(0,
-            cs="R2", clk="U3", miso="W2", mosi="V2", wp="Y2", hold="W1",
-            attrs=Attrs(IO_STANDARD="LVCMOS33")
-        ),
-
         Resource("eth_clk125",     0, Pins("L19", dir="i"),
                  Clock(125e6), Attrs(IO_TYPE="LVCMOS25")),
         Resource("eth_clk125_pll", 0, Pins("U16", dir="i"),
@@ -92,10 +87,10 @@ class VersaECP5Platform(LatticeECP5Platform):
             Subsignal("mdc",     Pins("G19", dir="o")),
             Subsignal("mdio",    Pins("H20", dir="io")),
             Subsignal("tx_clk",  Pins("C20", dir="o")),
-            Subsignal("tx_ctrl", Pins("E19", dir="o")),
+            Subsignal("tx_ctl",  Pins("E19", dir="o")),
             Subsignal("tx_data", Pins("J17 J16 D19 D20", dir="o")),
             Subsignal("rx_clk",  Pins("J19", dir="i")),
-            Subsignal("rx_ctrl", Pins("F19", dir="i")),
+            Subsignal("rx_ctl",  Pins("F19", dir="i")),
             Subsignal("rx_data", Pins("G18 G16 H18 H17", dir="i")),
             Attrs(IO_TYPE="LVCMOS25")
         ),
@@ -171,6 +166,31 @@ def toolchain_program(self, products, name):
             ])
 
 
+class VersaECP5Platform(_VersaECP5PlatformBase):
+    resources = (
+        _VersaECP5PlatformBase._resources +
+        [
+            *SPIFlashResources(0,
+                cs="R2", clk="U3", miso="V2", mosi="W2", wp="Y2", hold="W1",
+                attrs=Attrs(IO_STANDARD="LVCMOS33")
+            )
+        ]
+    )
+
+
+class VersaECP5Platform_USRMCLK(_VersaECP5PlatformBase):
+    resources = (
+        _VersaECP5PlatformBase._resources + 
+        [
+            # Note: after requesting from this platform, user should assign its clk
+            *SPIFlashResources(0,
+                cs="R2", clk=None, miso="V2", mosi="W2", wp="Y2", hold="W1",
+                attrs=Attrs(IO_STANDARD="LVCMOS33")
+            )
+        ]
+    )
+
+
 if __name__ == "__main__":
     from .test.blinky import *
     VersaECP5Platform().build(Blinky(), do_program=True)