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top_map.map
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'top'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off
-c 100 -o top_map.ncd top.ngd top.pcf
Target Device : xc3s400
Target Package : pq208
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Sat Nov 16 11:52:03 2019
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
WARNING:PhysDesignRules:812 - Dangling pin <DOB20> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB21> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB22> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB23> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB24> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB25> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB26> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB27> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB28> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB29> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB30> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB31> on
block:<Inst_num_decode_UP/Mrom_horizontal_rom000014.B>:<RAMB16_RAMB16B>.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 12
Logic Utilization:
Number of Slice Flip Flops: 105 out of 7,168 1%
Number of 4 input LUTs: 217 out of 7,168 3%
Logic Distribution:
Number of occupied Slices: 134 out of 3,584 3%
Number of Slices containing only related logic: 134 out of 134 100%
Number of Slices containing unrelated logic: 0 out of 134 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 238 out of 7,168 3%
Number used as logic: 185
Number used as a route-thru: 21
Number used as Shift registers: 32
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 29 out of 141 20%
IOB Flip Flops: 1
Number of RAMB16s: 4 out of 16 25%
Number of BUFGMUXs: 2 out of 8 25%
Average Fanout of Non-Clock Nets: 1.91
Peak Memory Usage: 4411 MB
Total REAL time to MAP completion: 0 secs
Total CPU time to MAP completion: 0 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "top_map.mrp" for details.