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RSP VU instruction delays not implemented #171

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clbr opened this issue Nov 5, 2020 · 2 comments

Contributor

clbr commented Nov 5, 2020

Load/store and register delays of the VU are not implemented. This leads to widely different timing vs hw.

Collaborator

tj90241 commented Dec 20, 2020

The emulated pipeline doesn't dual issue; that's the larger source of the timing issues.

Contributor Author

clbr commented Dec 20, 2020

That's #162 :)

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