uim_cmd.qmi

package uim;

const kIccidMaxSize = 20;

struct qmi_result {
  u16 result;
  u16 error;
};


struct card_result_t {
  u8 sw1;
  u8 sw2;
};

request open_logical_channel_req {
  required u8 slot = 0x01;
  optional u8 aid(u8 : kBufferDataSize) = 0x10;
} = 0x42;

response open_logical_channel_resp {
  required qmi_result result = 0x2;
  optional u8 channel_id = 0x10;
  optional card_result_t card_result = 0x11;
  optional u8 select_response(u8 : kBufferDataSize) = 0x12;
} = 0x42;


request reset_req {
} = 0x00;

response reset_resp {
  required qmi_result result = 0x2;
} = 0x00;


request send_apdu_req {
  required u8 slot = 0x01;
  required u8 apdu(u16 : kBufferDataSize) = 0x02;
  optional u8 channel_id = 0x10;
  optional u8 procedure_bytes = 0x11;
} = 0x3B;

response send_apdu_resp {
  required qmi_result result = 0x2;
  optional u8 apdu_response(u16 : kBufferDataSize) = 0x10;
} = 0x3B;


struct physical_slot_status {
  enum32 physical_card_status {
    kCardUnknown = 0,
    kCardAbsent = 1,
    kCardPresent = 2,
  };
  enum32 physical_slot_state {
    kSlotInactive = 0,
    kSlotActive = 1,
  };
  u8 logical_slot;
  u8 iccid(u8 : kIccidMaxSize);
};

struct slot_eid_info {
  u8 eid(u8 : 255);
};

struct physical_slot_info {
  u32 card_protocol;
  u8 num_app;
  u8 atr(u8 : 255);
  u8 is_euicc;
};

request get_slots_req {
} = 0x47;

response get_slots_resp {
  required qmi_result result = 0x2;
  optional physical_slot_status status(u8 : 10) = 0x10;
  optional physical_slot_info slot_info(u8 : 10) = 0x11;
  optional slot_eid_info eid_info(u8 : 10) = 0x12;
} = 0x47;


request switch_slot_req {
  required u8 logical_slot = 0x01;
  required u32 physical_slot = 0x02;
} = 0x46;

response switch_slot_resp {
  required qmi_result result = 0x2;
} = 0x46;