Firmware revision 13

Support for STM32L431 Support for HSE on STM32G071 HSE initialization timeout 10ms Optimize division where possible Add NEUTRON3 target Update ESCAPE4,SEQURE2 targets Cosmetics
neoxic · Feb 13, 2025 · 7102527 · 7102527
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commit 7102527
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Showing 26 changed files with 541 additions and 141 deletions.
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -59,7 +59,7 @@ add_target(EMAX1 STM32F051 DEAD_TIME=26 COMP_MAP=123 IO_PA2)
 add_target(ESCAPE1 STM32G071 DEAD_TIME=35 COMP_MAP=123 SENS_MAP=0xA5A4 VOLT_MUL=1100 CURR_MUL=30 LED_WS2812 LED_STAT IO_PA2 IO_AUX)
 add_target(ESCAPE2 STM32G071 DEAD_TIME=35 COMP_MAP=123 SENS_MAP=0xA6 VOLT_MUL=1100 BEC_MAP=0xADE IO_PA2)
 add_target(ESCAPE3 AT32F421 DEAD_TIME=66 COMP_MAP=123 SENS_MAP=0xA6 VOLT_MUL=1100 BEC_MAP=0xADE)
-add_target(ESCAPE4 STM32G071 DEAD_TIME=35 COMP_MAP=123 HALL_MAP=0xB358 SENS_MAP=0xA6A5A4 TEMP_SENS=NTC10K3455UP2K VOLT_MUL=1100 CURR_MUL=30 BEC_MAP=0xCEF LED_MAP=0xAF LED_STAT IO_PA2)
+add_target(ESCAPE4 STM32G071 DEAD_TIME=35 COMP_MAP=123 HALL_MAP=0xB358 SENS_MAP=0xA6A5A4 TEMP_SENS=NTC10K3455UP2K VOLT_MUL=1100 CURR_MUL=30 BEC_MAP=0xCEF LED_MAP=0xF2AF LED_STAT IO_PA2)
 add_target(FLYCOLOR1 STM32F051 DEAD_TIME=26 COMP_MAP=123 SENS_MAP=0xA6 VOLT_MUL=1100 LED_MAP=0xB5B4B3 IO_PA2)
 add_target(FLYCOLOR2 STM32G071 DEAD_TIME=35 COMP_MAP=123 SENS_MAP=0xA6 VOLT_MUL=1100 LED_MAP=0xB8 LED_STAT)
 add_target(GEPRC1 AT32F421 DEAD_TIME=66 COMP_MAP=123 SENS_MAP=0xA3 VOLT_MUL=1100)
@@ -80,10 +80,11 @@ add_target(LUMENIER1 GD32F350 DEAD_TIME=57 COMP_MAP=321 SENS_MAP=0xA3 VOLT_MUL=1
 add_target(LYI1 AT32F421 DEAD_TIME=66 COMP_MAP=321 SENS_MAP=0xA3 VOLT_MUL=1100)
 add_target(NEUTRON1 AT32F421 DEAD_TIME=66 COMP_MAP=321)
 add_target(NEUTRON2 AT32F421 DEAD_TIME=66 COMP_MAP=321 INVERTED_HIGH)
+add_target(NEUTRON3 STM32L431 DEAD_TIME=44 COMP_MAP=123 SENS_MAP=0xA6A3 VOLT_MUL=2100 CURR_MUL=125 USE_COMP2 USE_OPAMP)
 add_target(PHOTONDRIVE1 STM32G431 DEAD_TIME=180 COMP_MAP=132 SENS_MAP=0xBFA6 VOLT_MUL=1600 CURR_MUL=50 TEMP_CHAN=11 TEMP_FUNC=NTC10K3455LO10K LED_WS2812 LED_STAT USE_HSE=8 USE_PB1)
 add_target(RHINO1 STM32F051 DEAD_TIME=26 COMP_MAP=321 SENS_MAP=0xA6 VOLT_MUL=1100)
 add_target(SEQURE1 STM32G071 DEAD_TIME=35 COMP_MAP=123 SENS_MAP=0xA6A4 VOLT_MUL=2100 CURR_MUL=30 LED_WS2812 LED_STAT)
-add_target(SEQURE2 STM32G071 DEAD_TIME=50 COMP_MAP=123 SENS_MAP=0xA6A4 VOLT_MUL=2100 CURR_MUL=87 LED_WS2812 LED_STAT RPM_PIN=5)
+add_target(SEQURE2 STM32G071 DEAD_TIME=50 COMP_MAP=123 SENS_MAP=0xA6A4 VOLT_MUL=2100 CURR_MUL=87 LED_WS2812 LED_STAT RPM_PIN=5 USE_HSE=8)
 add_target(SKYSTARS1 GD32E230 DEAD_TIME=40 COMP_MAP=321 SENS_MAP=0xA3 VOLT_MUL=1100 LED_MAP=0xB5B3AF)
 add_target(TMOTOR1 STM32F051 DEAD_TIME=26 COMP_MAP=132 IO_PA2)
 add_target(TMOTOR2 STM32F051 DEAD_TIME=26 COMP_MAP=321)

diff --git a/README.md b/README.md
@@ -47,7 +47,7 @@ Use `LIBOPENCM3_DIR` to specify a path to LibOpenCM3 if it is not in the system
 
 ```
 git clone https://github.com/libopencm3/libopencm3.git
-make -C libopencm3 TARGETS='stm32/f0 stm32/g0 stm32/g4'
+make -C libopencm3 TARGETS='stm32/f0 stm32/g0 stm32/g4 stm32/l4'
 cmake -B build -D LIBOPENCM3_DIR=libopencm3
 ```
 

diff --git a/boot/src/io.c b/boot/src/io.c
@@ -34,7 +34,6 @@ void initio(void) {
 	GPIOA_PUPDR |= 0x80000000; // A15 (pull-down)
 	GPIOA_MODER &= ~0x40000000; // A15 (USART2_RX)
 	TIM1_ARR = CLK_CNT(20000) - 1;
-	TIM1_SR = ~TIM_SR_UIF;
 	TIM1_CR1 = TIM_CR1_CEN | TIM_CR1_OPM;
 	while (TIM1_CR1 & TIM_CR1_CEN) { // Wait for 50us high level on A15
 		if (!(GPIOA_IDR & 0x8000)) { // A15 low

diff --git a/boot/src/util.c b/boot/src/util.c
@@ -17,7 +17,7 @@
 
 #include "common.h"
 
-#ifdef STM32G4
+#ifndef FLASH_CR_STRT
 #define FLASH_CR_STRT FLASH_CR_START
 #endif
 
@@ -37,30 +37,30 @@ int write(char *dst, const char *src, int len) {
 	FLASH_CR = FLASH_CR_PER;
 	uint32_t ofs = ((uint32_t)dst + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); // Align upward to page boundary
 	for (int pos = 0; pos < len; pos += PAGE_SIZE) { // Erase pages
-#if defined STM32G0 || defined STM32G4
-		FLASH_CR = FLASH_CR_PER | FLASH_CR_STRT | ((ofs + pos - (uint32_t)_rom) / PAGE_SIZE) << FLASH_CR_PNB_SHIFT;
-#else
+#ifdef STM32F0
 		FLASH_AR = ofs + pos;
 		FLASH_CR = FLASH_CR_PER | FLASH_CR_STRT;
+#else
+		FLASH_CR = FLASH_CR_PER | FLASH_CR_STRT | ((ofs + pos - (uint32_t)_rom) / PAGE_SIZE) << FLASH_CR_PNB_SHIFT;
 #endif
 		while (FLASH_SR & FLASH_SR_BSY);
 	}
 	FLASH_CR = FLASH_CR_PG;
-#if defined STM32G0 || defined STM32G4
+#ifdef STM32F0
+	for (int pos = 0; pos < len; pos += 2) { // Write half-words
+		*(uint16_t *)(dst + pos) = *(uint16_t *)(src + pos);
+#else
 	for (int pos = 0; pos < len; pos += 8) { // Write double words
 		*(uint32_t *)(dst + pos) = *(uint32_t *)(src + pos);
 		*(uint32_t *)(dst + pos + 4) = *(uint32_t *)(src + pos + 4);
-#else
-	for (int pos = 0; pos < len; pos += 2) { // Write half-words
-		*(uint16_t *)(dst + pos) = *(uint16_t *)(src + pos);
 #endif
 		while (FLASH_SR & FLASH_SR_BSY);
 	}
 	FLASH_CR = FLASH_CR_LOCK;
-#if defined STM32G0 || defined STM32G4
-	if (FLASH_SR & (FLASH_SR_PROGERR | FLASH_SR_WRPERR)) return 0;
-#else
+#ifdef STM32F0
 	if (FLASH_SR & (FLASH_SR_PGERR | FLASH_SR_WRPRTERR)) return 0;
+#else
+	if (FLASH_SR & (FLASH_SR_PROGERR | FLASH_SR_WRPERR)) return 0;
 #endif
 	for (int pos = 0; pos < len; pos += 4) { // Check written data
 		if (*(uint32_t *)(dst + pos) != *(uint32_t *)(src + pos)) return 0;
@@ -81,14 +81,7 @@ void setwrp(int type) { // 0 - off, 1 - bootloader, 2 - full
 	FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
 	FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
 	FLASH_SR = -1; // Clear errors
-#if defined STM32G0 || defined STM32G4
-	FLASH_WRP1AR =
-		type == 1 ? (((_rom_end - _rom + 2047) >> 11) - 1) << 16:
-		type == 2 ? 0xff0000 : 0xff;
-	FLASH_CR = FLASH_CR_OPTSTRT;
-	while (FLASH_SR & FLASH_SR_BSY);
-	if (FLASH_SR & (FLASH_SR_PROGERR | FLASH_SR_WRPERR)) return;
-#else
+#ifdef STM32F0
 	char opts[6] = {FLASH_OPTION_BYTE_0, FLASH_OPTION_BYTE_1, FLASH_OPTION_BYTE_2, FLASH_OPTION_BYTE_3, 0xff, 0xff};
 	if (type == 1) opts[4] = ~((1 << ((_rom_end - _rom + 4095) >> 12)) - 1);
 	else if (type == 2) opts[4] = opts[5] = 0;
@@ -101,6 +94,13 @@ void setwrp(int type) { // 0 - off, 1 - bootloader, 2 - full
 		while (FLASH_SR & FLASH_SR_BSY);
 	}
 	if (FLASH_SR & (FLASH_SR_PGERR | FLASH_SR_WRPRTERR)) return;
+#else
+	FLASH_WRP1AR =
+		type == 1 ? (((_rom_end - _rom + 2047) >> 11) - 1) << 16:
+		type == 2 ? 0xff0000 : 0xff;
+	FLASH_CR = FLASH_CR_OPTSTRT;
+	while (FLASH_SR & FLASH_SR_BSY);
+	if (FLASH_SR & (FLASH_SR_PROGERR | FLASH_SR_WRPERR)) return;
 #endif
 #ifdef AT32F4
 	SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;

diff --git a/mcu/AT32F421/config.c b/mcu/AT32F421/config.c
@@ -27,9 +27,13 @@
 #define SENS_CHAN 0x66
 #endif
 
+#ifndef ANALOG_CHAN
+#define ANALOG_CHAN 0x2 // ADC_IN2 (PA2)
+#endif
+
 #ifndef TEMP_CHAN
-#define TEMP_CHAN 0x10 // CH16 (temp)
-#define TEMP_FUNC(x) (((x) - 1280) * 40 / 43 + 100)
+#define TEMP_CHAN 0x10 // ADC_IN16 (temp)
+#define TEMP_FUNC(x) ((((x) - 1280) * 3800 >> 12) + 100)
 #endif
 
 #define ADC1_BASE ADC_BASE
@@ -54,6 +58,7 @@ void init(void) {
 	RCC_CFGR &= ~RCC_CFGR_SW_PLL;
 	while (RCC_CFGR & RCC_CFGR_SWS_PLL);
 	RCC_CR &= ~RCC_CR_PLLON;
+	while (RCC_CR & RCC_CR_PLLRDY);
 	FLASH_ACR = 0x13; // LATENCY=3WS, PFTEN
 	RCC_CFGR = 0x2034c000; // ADCDIV=011 (PCLK/8), PLLMUL=011101 (x30)
 	RCC_CR |= RCC_CR_PLLON;
@@ -98,7 +103,6 @@ void init(void) {
 
 	ADC1_CR2 = ADC_CR2_ADON | ADC_CR2_TSVREFE;
 	TIM6_ARR = CLK_MHZ * 3 - 1;
-	TIM6_SR = ~TIM_SR_UIF;
 	TIM6_CR1 = TIM_CR1_CEN | TIM_CR1_OPM;
 	while (TIM6_CR1 & TIM_CR1_CEN); // Wait for 3us (RM 18.4.2.1)
 	ADC1_CR2 |= ADC_CR2_CAL;
@@ -109,10 +113,10 @@ void init(void) {
 	ADC1_SQR3 = SENS_CHAN;
 	len = SENS_CNT;
 	if (IO_ANALOG) {
-		ADC1_SQR3 |= AIN_CHAN << (len++ * 5);
+		ADC1_SQR3 |= ANALOG_CHAN << (len++ * 5);
 		ain = 1;
 	}
-	ADC1_SQR3 |= (TEMP_CHAN | 0x220) << (len * 5); // CH17 (vref)
+	ADC1_SQR3 |= (TEMP_CHAN | 0x220) << (len * 5); // ADC_IN17 (vref)
 	len += 2;
 	ADC1_SQR1 = (len - 1) << ADC_SQR1_L_LSB;
 #ifndef LED_WS2812

diff --git a/mcu/AT32F421/config.h b/mcu/AT32F421/config.h
@@ -19,7 +19,6 @@
 
 #define CLK 120000000
 #define IO_PA2
-#define XTIM TIM6
 
 #define IFTIM TIM3
 #define IFTIM_XRES 0

diff --git a/mcu/GD32E230/config.c b/mcu/GD32E230/config.c
@@ -25,9 +25,13 @@
 #define SENS_CHAN 0x6
 #endif
 
+#ifndef ANALOG_CHAN
+#define ANALOG_CHAN 0x2 // ADC_IN2 (PA2)
+#endif
+
 #ifndef TEMP_CHAN
-#define TEMP_CHAN 0x10 // CH16 (temp)
-#define TEMP_FUNC(x) ((1450 - (x)) * 40 / 43 + 100)
+#define TEMP_CHAN 0x10 // ADC_IN16 (temp)
+#define TEMP_FUNC(x) (((1450 - (x)) * 3800 >> 12) + 100)
 #endif
 
 #define ADC1_BASE ADC_BASE
@@ -49,6 +53,7 @@ void init(void) {
 	RCC_CFGR &= ~RCC_CFGR_SW_PLL;
 	while (RCC_CFGR & RCC_CFGR_SWS_PLL);
 	RCC_CR &= ~RCC_CR_PLLON;
+	while (RCC_CR & RCC_CR_PLLRDY);
 	FLASH_ACR = 0x12; // LATENCY=2WS, PFTEN
 	RCC_CFGR = 0x8040000; // PLLMUL=10001 (x18)
 	RCC_CR |= RCC_CR_PLLON;
@@ -95,7 +100,6 @@ void init(void) {
 	while (!(RCC_CR2 & RCC_CR2_HSI14RDY));
 	ADC1_CR2 = ADC_CR2_ADON | ADC_CR2_TSVREFE;
 	TIM6_ARR = CLK_MHZ - 1;
-	TIM6_SR = ~TIM_SR_UIF;
 	TIM6_CR1 = TIM_CR1_CEN | TIM_CR1_OPM;
 	while (TIM6_CR1 & TIM_CR1_CEN); // Wait for 1us (RM 10.4.1)
 	ADC1_CR2 |= ADC_CR2_CAL;
@@ -106,10 +110,10 @@ void init(void) {
 	ADC1_SQR3 = SENS_CHAN;
 	len = SENS_CNT;
 	if (IO_ANALOG) {
-		ADC1_SQR3 |= AIN_CHAN << (len++ * 5);
+		ADC1_SQR3 |= ANALOG_CHAN << (len++ * 5);
 		ain = 1;
 	}
-	ADC1_SQR3 |= (TEMP_CHAN | 0x220) << (len * 5); // CH17 (vref)
+	ADC1_SQR3 |= (TEMP_CHAN | 0x220) << (len * 5); // ADC_IN17 (vref)
 	len += 2;
 	ADC1_SQR1 = (len - 1) << ADC_SQR1_L_LSB;
 	DMA1_CPAR(1) = (uint32_t)&ADC1_DR;

diff --git a/mcu/GD32E230/config.h b/mcu/GD32E230/config.h
@@ -20,7 +20,6 @@
 #define CLK 72000000
 #define SW_BLANKING
 #define IO_PA2
-#define XTIM TIM6
 
 #define IFTIM TIM3
 #define IFTIM_XRES 0

diff --git a/mcu/GD32F350/config.c b/mcu/GD32F350/config.c
@@ -25,9 +25,13 @@
 #define SENS_CHAN 0xc0
 #endif
 
+#ifndef ANALOG_CHAN
+#define ANALOG_CHAN 0x2 // ADC_IN2 (PA2)
+#endif
+
 #ifndef TEMP_CHAN
-#define TEMP_CHAN 0x10 // CH16 (temp)
-#define TEMP_FUNC(x) ((1440 - (x)) * 400 / 408 + 100)
+#define TEMP_CHAN 0x10 // ADC_IN16 (temp)
+#define TEMP_FUNC(x) (((1440 - (x)) * 2000 >> 11) + 100)
 #endif
 
 #define ADC1_BASE ADC_BASE
@@ -54,6 +58,7 @@ void init(void) {
 	RCC_CFGR &= ~RCC_CFGR_SW_PLL;
 	while (RCC_CFGR & RCC_CFGR_SWS_PLL);
 	RCC_CR &= ~RCC_CR_PLLON;
+	while (RCC_CR & RCC_CR_PLLRDY);
 	RCC_CFGR = 0x8240000; // PLLMUL=11001 (x26)
 	RCC_CR |= RCC_CR_PLLON;
 	while (!(RCC_CR & RCC_CR_PLLRDY));
@@ -108,7 +113,6 @@ void init(void) {
 	while (!(RCC_CR2 & RCC_CR2_HSI14RDY));
 	ADC1_CR2 = ADC_CR2_ADON | ADC_CR2_TSVREFE;
 	TIM6_ARR = CLK_MHZ - 1;
-	TIM6_SR = ~TIM_SR_UIF;
 	TIM6_CR1 = TIM_CR1_CEN | TIM_CR1_OPM;
 	while (TIM6_CR1 & TIM_CR1_CEN); // Wait for 1us (RM 11.4.1)
 	ADC1_CR2 |= ADC_CR2_CAL;
@@ -119,10 +123,10 @@ void init(void) {
 	ADC1_SQR3 = SENS_CHAN;
 	len = SENS_CNT;
 	if (IO_ANALOG) {
-		ADC1_SQR3 |= AIN_CHAN << (len++ * 5);
+		ADC1_SQR3 |= ANALOG_CHAN << (len++ * 5);
 		ain = 1;
 	}
-	ADC1_SQR3 |= (TEMP_CHAN | 0x220) << (len * 5); // CH17 (vref)
+	ADC1_SQR3 |= (TEMP_CHAN | 0x220) << (len * 5); // ADC_IN17 (vref)
 	len += 2;
 	ADC1_SQR1 = (len - 1) << ADC_SQR1_L_LSB;
 	DMA1_CPAR(1) = (uint32_t)&ADC1_DR;

diff --git a/mcu/GD32F350/config.h b/mcu/GD32F350/config.h
@@ -19,7 +19,6 @@
 
 #define CLK 104000000
 #define SW_BLANKING
-#define XTIM TIM6
 
 #define IFTIM TIM2
 #define IFTIM_XRES 2

diff --git a/mcu/STM32F051/config.c b/mcu/STM32F051/config.c
@@ -29,11 +29,15 @@
 #define SENS_CHAN 0x48
 #endif
 
+#ifndef ANALOG_CHAN
+#define ANALOG_CHAN 0x2 // ADC_IN2 (PA2)
+#endif
+
 #ifdef TEMP_CHAN
 #define TEMP_SHIFT 12
 #else
 #define TEMP_SHIFT 0
-#define TEMP_CHAN 0x10000 // CH16 (temp)
+#define TEMP_CHAN 0x10000 // ADC_IN16 (temp)
 #define TEMP_FUNC(x) (((x) / 3300 - ST_TSENSE_CAL1_30C) * 320 / (ST_TSENSE_CAL2_110C - ST_TSENSE_CAL1_30C) + 120)
 #endif
 
@@ -103,10 +107,10 @@ void init(void) {
 	ADC1_CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_EXTEN_RISING_EDGE;
 	ADC1_SMPR = ADC_SMPR_SMP_239DOT5; // Sampling time ~17us @ HSI14
 	ADC1_CCR = ADC_CCR_VREFEN | ADC_CCR_TSEN;
-	ADC1_CHSELR = SENS_CHAN | TEMP_CHAN | 0x20000; // CH17 (vref)
+	ADC1_CHSELR = SENS_CHAN | TEMP_CHAN | 0x20000; // ADC_IN17 (vref)
 	len = SENS_CNT + 2;
 	if (IO_ANALOG) {
-		ADC1_CHSELR |= 1 << AIN_CHAN;
+		ADC1_CHSELR |= 1 << ANALOG_CHAN;
 		++len;
 		ain = 1;
 	}
@@ -173,7 +177,7 @@ void dma1_channel1_isr(void) {
 	DMA1_IFCR = DMA_IFCR_CTCIF(1);
 	DMA1_CCR(1) = 0;
 	int i = 0, u = 0, v = 0, c = 0, a = 0;
-#ifndef AIN_LAST
+#ifndef ANALOG_LAST
 	if (ain) a = buf[i++];
 #endif
 #ifdef SENS_SWAP
@@ -190,7 +194,7 @@ void dma1_channel1_isr(void) {
 #if SENS_CNT >= 3
 	u = buf[i++];
 #endif
-#ifdef AIN_LAST
+#ifdef ANALOG_LAST
 	if (ain) a = buf[i++];
 #endif
 	int r = ST_VREFINT_CAL * 3300 / buf[i + 1];

diff --git a/mcu/STM32F051/config.h b/mcu/STM32F051/config.h
@@ -19,7 +19,6 @@
 
 #define CLK 48000000
 #define SW_BLANKING
-#define XTIM TIM6
 
 #define IFTIM TIM2
 #define IFTIM_XRES 2