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false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtex7 + xilinx.com:vc707:part0:1.1 + + xc7vx485t + ffg1761 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chip/rtl/chip.v.pyv b/piton/design/chip/rtl/chip.v.pyv index 4b22ce5f8..fb9c56e2b 100644 --- a/piton/design/chip/rtl/chip.v.pyv +++ b/piton/design/chip/rtl/chip.v.pyv @@ -34,14 +34,17 @@ module chip( input impsel2, `endif // endif PITON_CHIP_FPGA -`ifdef PITON_FPGA_CLKS_GEN +`ifdef POLARA_VC707_CHIP + input core_ref_clk, + input io_clk, +`elsif PITON_FPGA_CLKS_GEN input clk_osc_p, input clk_osc_n, `else // ifndef PITON_FPGA_CLKS_GEN // Input clocks input core_ref_clk, input io_clk, -`endif // endif PITON_FPGA_CLKS_GEN +`endif // endif POLARA_VC707_CHIP, PITON_FPGA_CLKS_GEN // Resets // reset is assumed to be asynchronous @@ -83,14 +86,27 @@ module chip( output piton_prsnt_n, output piton_ready_n, + // No need for the vc707 chip that works with the genesys2 chipset (Polara project) +`ifndef POLARA_VC707_CHIP input chipset_prsnt_n, +`endif // endif POLARA_VC707_CHIP output [7:0] leds, + `endif // endif PITON_CHIP_FPGA `ifndef PITON_NO_CHIP_BRIDGE // For FPGA implementations, we convert to differential and source synchronous -`ifdef PITON_CHIP_FPGA +`ifdef POLARA_VC707_CHIP + // Virtual channel credit-based off-chip interface + input [31:0] intf_chip_data, + input [1:0] intf_chip_channel, + output [2:0] intf_chip_credit_back, + + output [31:0] chip_intf_data, + output [1:0] chip_intf_channel, + input [2:0] chip_intf_credit_back +`elsif PITON_CHIP_FPGA output chip_intf_clk_p, output chip_intf_clk_n, input intf_chip_clk_p, @@ -118,7 +134,7 @@ module chip( output [31:0] chip_intf_data, output [1:0] chip_intf_channel, input [2:0] chip_intf_credit_back -`endif // endif PITON_CHIP_FPGA +`endif // endif POLARA_VC707_CHIP, PITON_CHIP_FPGA `else // ifdef PITON_NO_CHIP_BRIDGE output processor_offchip_noc1_valid, output [`NOC_DATA_WIDTH-1:0] processor_offchip_noc1_data, @@ -185,6 +201,7 @@ module chip( wire oram_dummy_gen; `endif // endif PITON_CHIP_FPGA // Same for generating clocks +`ifndef POLARA_VC707_CHIP `ifdef PITON_FPGA_CLKS_GEN wire core_ref_clk; @@ -204,6 +221,7 @@ module chip( wire [2:0] chip_intf_credit_back; `endif // endif PITON_CHIP_FPGA `endif // endif PITON_NO_CHIP_BRIDGE +`endif // endif POLARA_VC707_CHIP // OCI internal wires @@ -352,6 +370,9 @@ module chip( `endif // ifdef PITON_RV64_PLIC `endif // ifdef PITON_RV64_PLATFORM + reg [`PITON_NUM_TILES-1:0] timer_irq_reg_i; + reg [`PITON_NUM_TILES*2-1:0] irq_reg_i; + // Tiles JTAG interface wire jtag_tiles_ucb_val; wire [`UCB_BUS_WIDTH-1:0] jtag_tiles_ucb_data; @@ -538,7 +559,9 @@ module chip( assign piton_ready_n = ~rst_n_inter_sync; `ifdef PITON_FPGA_CLKS_GEN +`ifndef POLARA_VC707_CHIP assign leds[0] = mmcm_locked; +`endif // endif POLARA_VC707_CHIP `else // ifndef PITON_FPGA_CLKS_GEN assign leds[0] = 1'b1; `endif // endif PITON_FPGA_CLKS_GEN @@ -667,6 +690,7 @@ module chip( ///////////////////////// // Need to generate clocks from MMCM for standalone chip FPGA synthesis +`ifndef POLARA_VC707_CHIP `ifdef PITON_FPGA_CLKS_GEN // Generate core_ref_clk clk_mmcm_chip clk_mmcm ( @@ -679,7 +703,9 @@ module chip( .core_ref_clk(core_ref_clk) ); `endif // endif PITON_FPGA_CLKS_GEN +`endif // endif POLARA_VC707_CHIP +`ifndef POLARA_VC707_CHIP `ifndef PITON_NO_CHIP_BRIDGE `ifdef PITON_CHIP_FPGA // Generate io_clk from input @@ -728,6 +754,7 @@ module chip( ); `endif // endif PITON_CHIP_FPGA `endif // endif PITON_NO_CHIP_BRIDGE +`endif // endif POLARA_VC707_CHIP // Off-Chip Interface Block // Removed, the top level I/Os are in the backend dir @@ -1084,11 +1111,11 @@ module chip( ,.unavailable_o ( unavailable[_FLAT_ID_] ) `endif // ifdef PITON_RV64_DEBUGUNIT `ifdef PITON_RV64_CLINT - ,.timer_irq_i ( timer_irq[_FLAT_ID_] ) + ,.timer_irq_i ( timer_irq_reg_i[_FLAT_ID_] ) ,.ipi_i ( ipi[_FLAT_ID_] ) `endif // ifdef PITON_RV64_CLINT `ifdef PITON_RV64_PLIC - ,.irq_i ( irq[_FLAT_ID_*2 +: 2] ) + ,.irq_i ( irq_reg_i[_FLAT_ID_*2 +: 2] ) `endif // ifdef PITON_RV64_PLIC `endif // ifdef PITON_RV64_PLATFORM , @@ -1278,12 +1305,17 @@ pmesh_rvic pmesh_rvic ( .unavailable_i ( unavailable ), .tck_i ( jtag_clk_inter ), .tms_i ( jtag_modesel_inter ), - .trst_ni ( jtag_rst_l_inter_sync ), + .trst_ni ( jtag_rst_l_inter_sync ), .td_i ( jtag_datain_inter ), .td_o ( jtag_dataout_inter ), .tdo_oe_o ( ) // not used ); +always @(posedge clk_muxed) begin + timer_irq_reg_i <= timer_irq; + irq_reg_i <= irq; +end + endmodule `endif diff --git a/piton/design/chip/xilinx/vc707/constraints.xdc b/piton/design/chip/xilinx/vc707/constraints.xdc new file mode 100644 index 000000000..32d67f099 --- /dev/null +++ b/piton/design/chip/xilinx/vc707/constraints.xdc @@ -0,0 +1,274 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# Clock signals +#set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_p] +#set_property PACKAGE_PIN E19 [get_ports chipset_clk_osc_p] +#set_property PACKAGE_PIN E18 [get_ports chipset_clk_osc_n] +#set_property IOSTANDARD LVDS [get_ports chipset_clk_osc_n] +#set_property IOSTANDARD LVDS [get_ports clk_osc_p] +#set_property PACKAGE_PIN E19 [get_ports clk_osc_p] +#set_property PACKAGE_PIN E18 [get_ports clk_osc_n] +#set_property IOSTANDARD LVDS [get_ports clk_osc_n] + +#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets chipset/clk_mmcm/inst/clk_in1_clk_mmcm] + +# Reset +set_property IOSTANDARD LVCMOS18 [get_ports rst_n] +set_property PACKAGE_PIN C39 [get_ports rst_n] + +# False paths +#set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*] +#set_false_path -to [get_cells -hierarchical *ui_clk_sync_rst_r*] +#set_false_path -to [get_cells -hierarchical *ui_clk_syn_rst_delayed*] +#set_false_path -to [get_cells -hierarchical *init_calib_complete_f*] +#set_false_path -to [get_cells -hierarchical *chipset_rst_n*] +#set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] + +#set_clock_groups -name sync_gr1 -logically_exclusive -group chipset_clk_clk_mmcm -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] + +# UART +#IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property IOSTANDARD LVCMOS18 [get_ports uart_tx] +#set_property PACKAGE_PIN AU36 [get_ports uart_tx] +#set_property IOSTANDARD LVCMOS18 [get_ports uart_rx] +#set_property PACKAGE_PIN AU33 [get_ports uart_rx] + +# Switches +#set_property PACKAGE_PIN AV30 [get_ports sw[0]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[0]] +#set_property PACKAGE_PIN AY33 [get_ports sw[1]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[1]] +#set_property PACKAGE_PIN BA31 [get_ports sw[2]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[2]] +#set_property PACKAGE_PIN BA32 [get_ports sw[3]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[3]] +#set_property PACKAGE_PIN AW30 [get_ports sw[4]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[4]] +#set_property PACKAGE_PIN AY30 [get_ports sw[5]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[5]] +#set_property PACKAGE_PIN BA30 [get_ports sw[6]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[6]] +#set_property PACKAGE_PIN BB31 [get_ports sw[7]] +#set_property IOSTANDARD LVCMOS18 [get_ports sw[7]] + +# SD +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AN30 DRIVE 16 SLEW FAST} [get_ports sd_clk_out] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AP30} [get_ports sd_cmd] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AR30} [get_ports {sd_dat[0]}] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AU31} [get_ports {sd_dat[1]}] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AV31} [get_ports {sd_dat[2]}] +#set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN AT30} [get_ports {sd_dat[3]}] +# set_property IOSTANDARD LVCMOS18 [get_ports sd_cd] +# set_property PACKAGE_PIN AP32 [get_ports sd_cd] + +#set_property PACKAGE_PIN AV30 [get_ports uart_lb_sw] +#set_property IOSTANDARD LVCMOS18 [get_ports uart_lb_sw] + +## LEDs + +set_property PACKAGE_PIN AM39 [get_ports leds[0]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[0]] +set_property PACKAGE_PIN AN39 [get_ports leds[1]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[1]] +set_property PACKAGE_PIN AR37 [get_ports leds[2]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[2]] +set_property PACKAGE_PIN AT37 [get_ports leds[3]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[3]] +set_property PACKAGE_PIN AR35 [get_ports leds[4]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[4]] +set_property PACKAGE_PIN AP41 [get_ports leds[5]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[5]] +set_property PACKAGE_PIN AP42 [get_ports leds[6]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[6]] +set_property PACKAGE_PIN AU39 [get_ports leds[7]] +set_property IOSTANDARD LVCMOS18 [get_ports leds[7]] + +############################################# +# SD Card Constraints for 25MHz +############################################# +#create_generated_clock -name sd_fast_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] +#create_generated_clock -name sd_slow_clk -source [get_pins chipset/clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset/chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] +#create_generated_clock -name sd_clk_out -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] +#create_generated_clock -name sd_clk_out_1 -source [get_pins chipset/sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] + +# compensate for board trace uncertainty +#set_clock_uncertainty 0.500 [get_clocks sd_clk_out] +#set_clock_uncertainty 0.500 [get_clocks sd_clk_out_1] + +################# +# FPGA out / card in +# data is aligned with clock (source synchronous) + +# hold fast (spec requires minimum 2ns), note that data is launched on falling edge, so 0.0 is ok here +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay -6.000 [get_ports sd_cmd] + +# setup fast (spec requires minimum 6ns) +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 8.000 [get_ports sd_cmd] + +# hold slow (spec requires minimum 5ns), note that data is launched on falling edge, so 0.0 is ok here +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay -8.000 [get_ports sd_cmd] + +# setup slow (spec requires minimum 5ns) +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 8.000 [get_ports sd_cmd] + +################# +# card out / FPGA in +# data is launched on negative clock edge here + +# propdelay fast +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] + +# contamination delay fast +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] + +# propdelay slow +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -max -add_delay 14.000 [get_ports sd_cmd] + +# contamination slow +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks sd_clk_out_1] -clock_fall -min -add_delay -14.000 [get_ports sd_cmd] + +################# +# clock groups + +#set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] +#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks sd_fast_clk] -group [get_clocks -include_generated_clocks sd_slow_clk] +#set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks chipset_clk_clk_mmcm] -group [get_clocks -filter { NAME =~ "*sd*" }] + +############################################# +# FMC +############################################# +# Clock signals from chipset + +# 66.6667MHz +#create_clock -period 14.9999993 -name io_clk -waveform {0.000 7.49999965} [get_ports io_clk] +#create_clock -period 14.9999993 -name core_ref_clk -waveform {0.000 7.49999965} [get_ports core_ref_clk] +# 64MHz +#create_clock -period 15.625 -name io_clk -waveform {0.000 7.8125} [get_ports io_clk] +#create_clock -period 15.625 -name core_ref_clk -waveform {0.000 7.8125} [get_ports core_ref_clk] +# 50MHz +create_clock -period 20 -name io_clk -waveform {0.000 10} [get_ports io_clk] +create_clock -period 20 -name core_ref_clk -waveform {0.000 10} [get_ports core_ref_clk] +# Needed to pass placement (2024/07/08 RR) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {io_clk_IBUF}] +set_property -dict {PACKAGE_PIN C38 IOSTANDARD LVCMOS18} [get_ports io_clk] +set_property -dict {PACKAGE_PIN E33 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] + +#[Place 30-876] Port 'core_ref_clk' is assigned to PACKAGE_PIN 'L40' which can only be used as the N side of a differential clock input. +#Please use the following constraint(s) to pass this DRC check: +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {core_ref_clk_IBUF}] + +set_property -dict {PACKAGE_PIN L31 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[1]] +set_property -dict {PACKAGE_PIN K32 IOSTANDARD LVCMOS18} [get_ports chip_intf_channel[0]] + +#set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] + +set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[2]] +set_property -dict {PACKAGE_PIN L32 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[1]] +set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVCMOS18} [get_ports chip_intf_credit_back[0]] + +set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[1]] +set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports intf_chip_channel[0]] + +set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[31]] +set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[30]] +set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[29]] +set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[28]] +set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[27]] +set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[26]] +set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[25]] +set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[24]] +set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[23]] +set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[22]] +set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[21]] +set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[20]] +set_property -dict {PACKAGE_PIN M31 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[19]] +set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[18]] +set_property -dict {PACKAGE_PIN B33 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[17]] +set_property -dict {PACKAGE_PIN B32 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[16]] +set_property -dict {PACKAGE_PIN A34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[15]] +set_property -dict {PACKAGE_PIN B34 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[14]] +set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[13]] +set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[12]] +set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[11]] +set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[10]] +set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[9]] +set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[8]] +set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[7]] +set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[6]] +set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[5]] +set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[4]] +set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[3]] +set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[2]] +set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[1]] +set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports intf_chip_data[0]] + +set_property -dict {PACKAGE_PIN A37 IOSTANDARD LVCMOS18} [get_ports piton_prsnt_n] +set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18} [get_ports piton_ready_n] + +set_property -dict {PACKAGE_PIN A36 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[31]] +set_property -dict {PACKAGE_PIN A35 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[30]] +set_property -dict {PACKAGE_PIN F37 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[29]] +set_property -dict {PACKAGE_PIN F36 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[28]] +set_property -dict {PACKAGE_PIN E39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[27]] +set_property -dict {PACKAGE_PIN F39 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[26]] +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[25]] +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[24]] +set_property -dict {PACKAGE_PIN V31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[23]] +set_property -dict {PACKAGE_PIN V30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[22]] +set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[21]] +set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[20]] +set_property -dict {PACKAGE_PIN P31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[19]] +set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[18]] +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[17]] +set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[16]] +set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[15]] +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[14]] +set_property -dict {PACKAGE_PIN T31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[13]] +set_property -dict {PACKAGE_PIN U31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[12]] +set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[11]] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[10]] +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[9]] +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[8]] +set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[7]] +set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[6]] +set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[5]] +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[4]] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[3]] +set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[2]] +set_property -dict {PACKAGE_PIN N31 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[1]] +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS18} [get_ports chip_intf_data[0]] + +set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[2]] +set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[1]] +set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports intf_chip_credit_back[0]] diff --git a/piton/design/chip/xilinx/vc707/devices.xml b/piton/design/chip/xilinx/vc707/devices.xml new file mode 100644 index 000000000..f0e70024c --- /dev/null +++ b/piton/design/chip/xilinx/vc707/devices.xml @@ -0,0 +1,66 @@ + + + + + chip + + + + mem + 0x0 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + sd + 0xf000000000 + + 0xff0300000 + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + diff --git a/piton/design/chip/xilinx/vc707/devices_ariane.xml b/piton/design/chip/xilinx/vc707/devices_ariane.xml new file mode 100644 index 000000000..b86978353 --- /dev/null +++ b/piton/design/chip/xilinx/vc707/devices_ariane.xml @@ -0,0 +1,84 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + sd + 0xf000000000 + + 0xff0300000 + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + + + + ariane_debug + 0xfff1000000 + 0x1000 + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + + ariane_clint + 0xfff1020000 + 0xc0000 + + + + + ariane_plic + 0xfff1100000 + 0x4000000 + + + + + diff --git a/piton/design/chip/xilinx/vc707/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci b/piton/design/chip/xilinx/vc707/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci new file mode 100644 index 000000000..6e96ea80e --- /dev/null +++ b/piton/design/chip/xilinx/vc707/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci @@ -0,0 +1,713 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_mmcm_chip + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 100.0 + 0000 + 0000 + 66.66667 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 66.66667 + 0.000 + 50.000 + 66.666 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + core_ref_clk + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + 0.1111111111111111 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________200____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 3.000 + 0.000 + FALSE + 5.0 + 10.0 + 9.000 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 64.000 + 2.000 + 1 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + core_ref_clk__66.66667______0.000______50.0______117.498____105.563 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 200 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1440.000 + 600.000 + clk_mmcm_chip + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 0.010 + 100.0 + 0.010 + BUFG + 117.498 + false + 105.563 + 50.000 + 66.666 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + core_ref_clk + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_mmcm_chip + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 3.000 + 0.000 + false + 5.0 + 10.0 + 9.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 1 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 200 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + virtex7 + xilinx.com:vc707:part0:1.1 + + xc7vx485t + ffg1761 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 8 + TRUE + ../../../../vc707_chip.gen/sources_1/ip/clk_mmcm_chip + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/include/chipset_define.vh b/piton/design/chipset/include/chipset_define.vh index 026d98494..a9f039827 100644 --- a/piton/design/chipset/include/chipset_define.vh +++ b/piton/design/chipset/include/chipset_define.vh @@ -82,8 +82,13 @@ `define ADDR_TRANS_PHYS_WIDTH_ALIGN 4 `define ADDR_TRANS_SECTION_MULT 4 `elsif GENESYS2_BOARD // 32-bit PHY + `ifdef POLARA_GEN2_CHIPSET + `define ADDR_TRANS_PHYS_WIDTH_ALIGN 6 + `define ADDR_TRANS_SECTION_MULT 2 + `else `define ADDR_TRANS_PHYS_WIDTH_ALIGN 5 `define ADDR_TRANS_SECTION_MULT 2 + `endif `else // 64-bit interface by default `define ADDR_TRANS_PHYS_WIDTH_ALIGN 6 `define ADDR_TRANS_SECTION_MULT 1 diff --git a/piton/design/chipset/include/mc_define.h b/piton/design/chipset/include/mc_define.h index 133877099..15edf8ef5 100644 --- a/piton/design/chipset/include/mc_define.h +++ b/piton/design/chipset/include/mc_define.h @@ -105,6 +105,25 @@ `define DDR3_CS_WIDTH 2 `define DDR3_BG_WIDTH 2 `define DDR3_ODT_WIDTH 2 +`elsif ALVEO_BOARD + `define BOARD_MEM_SIZE_MB 8192 + `define WORDS_PER_BURST 8 + `define WORD_SIZE 8 // in bytes + `define MIG_APP_ADDR_WIDTH 32 + `define MIG_APP_CMD_WIDTH 3 + `define MIG_APP_DATA_WIDTH 512 + `define MIG_APP_MASK_WIDTH 64 + + `define DDR3_DQ_WIDTH 72 + `define DDR3_DQS_WIDTH 18 + `define DDR3_ADDR_WIDTH 17 + `define DDR3_BA_WIDTH 2 + `define DDR3_DM_WIDTH 0 + `define DDR3_CK_WIDTH 1 + `define DDR3_CKE_WIDTH 1 + `define DDR3_CS_WIDTH 1 + `define DDR3_BG_WIDTH 2 + `define DDR3_ODT_WIDTH 1 `elsif NEXYS4DDR_BOARD `define BOARD_MEM_SIZE_MB 256 `define WORDS_PER_BURST 8 diff --git a/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v b/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v index ae747e8c0..08dad8596 100644 --- a/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v +++ b/piton/design/chipset/io_ctrl/rtl/int_pkt_gen.v @@ -178,7 +178,7 @@ always @(*) begin pkt_flit1[63:50] = chip_id; pkt_flit1[49:42] = x_pos; pkt_flit1[41:34] = y_pos; - pkt_flit1[33:30] = 4'b0; // processor + pkt_flit1[33:30] = 4'h5; // processor pkt_flit1[29:22] = 8'b1; if (NOC_ID == 1) begin pkt_flit1[21:14] = `MSG_TYPE_INTERRUPT_FWD; // interrupt forward diff --git a/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci new file mode 100644 index 000000000..446f476c3 --- /dev/null +++ b/piton/design/chipset/io_ctrl/xilinx/alveou280/ip_cores/uart_16550/uart_16550.xci @@ -0,0 +1,142 @@ + + + xilinx.com + xci + unknown + 1.0 + + + uart_16550 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 25000000 + virtexuplushbm + 0 + 0 + 1 + VERSAL_AI_CORE_ES1 + 50000000 + 1 + 25000000 + 25 + 0 + 0 + 16550 + 50000000 + 50 + 1 + 1 + uart_16550 + Custom + false + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 26 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci index c39a5b875..e3f12e2ae 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/atg_uart_init.xci @@ -7,10 +7,284 @@ atg_uart_init - + 65536 + 100000000 + 0 + 0 + 0.0 + 1 + 1 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + WRITE_ONLY + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 0 0 4 @@ -23,15 +297,16 @@ 1 0 16 - 0x0000000013A00FFF + 0x0000000013A00000 0x0000000013A00FFF 3 0 - 0x0000000013A00FFF - 0x0000000013A00FFF + 0x0000000012A00000 + 0x0000000012A00FFF 3 0 16 + no_mem_file_loaded 0 1 0 @@ -47,10 +322,10 @@ 0x00000400 256 1 - atg_uart_init_addr.mif - atg_uart_init_ctrl.mif - atg_uart_init_data.mif - atg_uart_init_mask.mif + atg_uart_init_addr.mem + atg_uart_init_ctrl.mem + atg_uart_init_data.mem + atg_uart_init_mask.mem "00000000000000000000000000000001" 0 5000 @@ -74,25 +349,30 @@ 32 1 0 - atg_uart_init_default_addrram.mif - atg_uart_init_default_cmdram.mif + atg_uart_init_default_addrram.mem + atg_uart_init_default_cmdram.mem NONE NONE NONE - atg_uart_init_default_prmram.mif - atg_uart_init_default_mstram.mif + atg_uart_init_default_prmram.mem + atg_uart_init_default_mstram.mem + 0 254 0xABCD 8 8 32 1 + 0 1 + Seed_Based 100 Read_Write 16 16 Custom + no_mem_file_loaded + 0 0x5A5A 0x7C9B 16 @@ -197,25 +477,176 @@ 8 1080 kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 12 + 10 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe index 6c8df1dfe..b4b7e995f 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/atg_uart_init/uart_data.coe @@ -1,2 +1,2 @@ memory_initialization_radix=16; -memory_initialization_vector=00000080 00000024 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; +memory_initialization_vector=00000080 00000004 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci index 84904252b..1c4658573 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_16384x512/bram_16384x512.xci @@ -7,9 +7,89 @@ bram_16384x512 - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.0 + 0 14 14 1 @@ -60,6 +140,8 @@ 1 16384 16384 + 1 + 1 512 512 0 @@ -126,6 +208,8 @@ 8kx2 false false + 1 + 1 512 512 false @@ -154,28 +238,64 @@ false Stand_Alone kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 4 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -194,6 +314,16 @@ + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci index 124a0ffde..b1ad2f3a4 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/bram_256x512/bram_256x512.xci @@ -7,9 +7,89 @@ bram_256x512 - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.0 + 0 8 8 1 @@ -60,6 +140,8 @@ 1 256 256 + 1 + 1 512 512 0 @@ -126,6 +208,8 @@ 8kx2 false false + 1 + 1 512 512 false @@ -154,28 +238,64 @@ false Stand_Alone kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 4 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -194,6 +314,16 @@ + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci index e9e2c882b..9f04da0aa 100644 --- a/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci +++ b/piton/design/chipset/io_ctrl/xilinx/genesys2/ip_cores/uart_16550/uart_16550.xci @@ -9,51 +9,131 @@ uart_16550 + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 25000000 kintex7 0 0 1 - 66667000 + VERSAL_AI_CORE_ES1 + 40000000 1 25000000 25 0 0 16550 - 66667000 - 66.667 + 40000000 + 40 1 1 uart_16550 Custom false kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 13 + 26 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe b/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe index b35ea84ba..aec4227ff 100644 --- a/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe +++ b/piton/design/chipset/io_ctrl/xilinx/vc707/ip_cores/atg_uart_init/uart_data.coe @@ -1,2 +1,2 @@ memory_initialization_radix=16; -memory_initialization_vector=00000080 00000021 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; +memory_initialization_vector=00000080 0000001b 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000; diff --git a/piton/design/chipset/mc/rtl/gen2_polara_top.sv b/piton/design/chipset/mc/rtl/gen2_polara_top.sv new file mode 100644 index 000000000..59d34b0fb --- /dev/null +++ b/piton/design/chipset/mc/rtl/gen2_polara_top.sv @@ -0,0 +1,466 @@ +// ------------------------------------------------------------------------------- +// Project: core-v-polara-apu +// File: gen2_polara_top.sv +// Author: Raphael Rowley +// Creation Date: 2024/06/12 +// +// Description: +// Memory controller top level for chipset on the genesys2 to communicate with +// the Polara ASIC. +// +// ------------------------------------------------------------------------------- + +`include "mc_define.h" +`include "noc_axi4_bridge_define.vh" + +module gen2_polara_top( + + // DDR3 Physical Interface + output logic [`DDR3_ADDR_WIDTH-1:0] ddr3_sdram_addr, + output logic [`DDR3_BA_WIDTH-1:0] ddr3_sdram_ba, + output logic ddr3_sdram_cas_n, + output logic [`DDR3_CK_WIDTH-1:0] ddr3_sdram_ck_n, + output logic [`DDR3_CK_WIDTH-1:0] ddr3_sdram_ck_p, + output logic [`DDR3_CKE_WIDTH-1:0] ddr3_sdram_cke, + output logic [`DDR3_CS_WIDTH-1:0] ddr3_sdram_cs_n, + inout logic [`DDR3_DM_WIDTH-1:0] ddr3_sdram_dm, + inout logic [`DDR3_DQ_WIDTH-1:0] ddr3_sdram_dq, + inout logic [`DDR3_DQS_WIDTH-1:0] ddr3_sdram_dqs_n, + inout logic [`DDR3_DQS_WIDTH-1:0] ddr3_sdram_dqs_p, + output logic [`DDR3_ODT_WIDTH-1:0] ddr3_sdram_odt, + output logic ddr3_sdram_ras_n, + output logic ddr3_sdram_reset_n, + output logic ddr3_sdram_we_n, + + // Clocks and reset + input logic chipset_clk, + input logic sys_rst_n, +`ifndef POLARA_GEN2_CHIPSETSE + input logic mig_ddr3_sys_diff_clock_clk_n, + input logic mig_ddr3_sys_diff_clock_clk_p, +`else + input logic mig_ddr3_sys_se_clock_clk, + + // Polara ASIC Control Signals + output logic chip_async_mux, + output logic chip_clk_en, + output logic chip_clk_mux_sel, + output logic chip_rst_n, + output logic fll_rst_n, + output logic fll_bypass, + input logic fll_clkdiv, + input logic fll_lock, + output logic fll_cfg_req, + output logic fll_opmode, + output logic [3:0] fll_range, +`endif + + + // NOC + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , + + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy , + + // Others + output logic init_calib_complete_out, + output logic mem_ui_clk_sync_rst, + + // UART + input logic uart_boot_en + +); + // ------------------------------------------------------------------------------- + // Signal declarations + // ------------------------------------------------------------------------------- + logic trans_fifo_val; + logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + logic trans_fifo_rdy; + + + + logic fifo_trans_val; + logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + logic fifo_trans_rdy; + + logic ui_clk; + logic noc_axi4_bridge_rst; + logic noc_axi4_bridge_init_done; + + + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_arid; + logic [`AXI4_ADDR_WIDTH -1:0] ddr3_axi_araddr; + logic [`AXI4_BURST_WIDTH -1:0] ddr3_axi_arburst; + logic [`AXI4_CACHE_WIDTH -1:0] ddr3_axi_arcache; + logic [`AXI4_LEN_WIDTH -1:0] ddr3_axi_arlen; + logic ddr3_axi_arlock; + logic [`AXI4_PROT_WIDTH -1:0] ddr3_axi_arprot; + logic [`AXI4_QOS_WIDTH -1:0] ddr3_axi_arqos; + logic ddr3_axi_arready; + logic [`AXI4_SIZE_WIDTH -1:0] ddr3_axi_arsize; + logic ddr3_axi_arvalid; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_arregion; // not used + logic [`AXI4_USER_WIDTH -1:0] m_axi_aruser; // not used + + + + logic [`AXI4_ADDR_WIDTH -1:0] ddr3_axi_awaddr; + logic [`AXI4_BURST_WIDTH -1:0] ddr3_axi_awburst; + logic [`AXI4_CACHE_WIDTH -1:0] ddr3_axi_awcache; + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_awid; + logic [`AXI4_LEN_WIDTH -1:0] ddr3_axi_awlen; + logic ddr3_axi_awlock; + logic [`AXI4_PROT_WIDTH -1:0] ddr3_axi_awprot; + logic [`AXI4_QOS_WIDTH -1:0] ddr3_axi_awqos; + logic ddr3_axi_awready; + logic [`AXI4_SIZE_WIDTH -1:0] ddr3_axi_awsize; + logic ddr3_axi_awvalid; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_awregion; // not used + logic [`AXI4_USER_WIDTH -1:0] m_axi_awuser; // not used + + + + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_bid; + logic ddr3_axi_bready; + logic [`AXI4_RESP_WIDTH -1:0] ddr3_axi_bresp; + logic ddr3_axi_bvalid; + logic [`AXI4_USER_WIDTH -1:0] m_axi_buser; // not used + + + logic [`AXI4_DATA_WIDTH -1:0] ddr3_axi_rdata; + logic [`AXI4_ID_WIDTH -1:0] ddr3_axi_rid; + logic ddr3_axi_rlast; + logic ddr3_axi_rready; + logic [`AXI4_RESP_WIDTH -1:0] ddr3_axi_rresp; + logic ddr3_axi_rvalid; + logic [`AXI4_USER_WIDTH -1:0] m_axi_ruser; // not used + + + logic [`AXI4_DATA_WIDTH -1:0] ddr3_axi_wdata; + logic ddr3_axi_wlast; + logic ddr3_axi_wready; + logic [`AXI4_STRB_WIDTH -1:0] ddr3_axi_wstrb; + logic ddr3_axi_wvalid; + logic [`AXI4_ID_WIDTH -1:0] m_axi_wid; // not used + logic [`AXI4_USER_WIDTH -1:0] m_axi_wuser; // not used + + logic mig_ddr3_ui_clk; + + logic ui_clk_sync_rst_r; + logic ui_clk_sync_rst_r_r; + logic [31:0] delay_cnt; + logic core_ref_clk; + logic ui_clk_syn_rst_delayed; + + logic afifo_rst_1; + logic afifo_ui_rst_r; + logic afifo_ui_rst_r_r; + logic ui_clk_sync_rst; + logic afifo_rst_2; + + logic init_calib_complete; + + logic [1:0] polara_gen2chipset_bus_i; + logic [11:0] polara_gen2chipset_bus_o; + + // ------------------------------------------------------------------------------- + // Behavioral + // ------------------------------------------------------------------------------- + + // from mc_top.v + assign init_calib_complete = noc_axi4_bridge_init_done; + assign init_calib_complete_out = init_calib_complete & ~ui_clk_syn_rst_delayed; + + // ------------------------------------------------------------------------------- + // rst logic taken from mc_top.v + // ------------------------------------------------------------------------------- + + // needed for correct rst of async fifo + + always @(posedge core_ref_clk) begin + ui_clk_sync_rst_r <= ui_clk_sync_rst; + ui_clk_sync_rst_r_r <= ui_clk_sync_rst_r; + end + + always @(posedge core_ref_clk) begin + if (~sys_rst_n) + delay_cnt <= 32'h1ff; + else begin + delay_cnt <= (delay_cnt != 0) & ~ui_clk_sync_rst_r_r ? delay_cnt - 1 : delay_cnt; + end + end + + assign core_ref_clk = chipset_clk; + always @(posedge core_ref_clk) begin + if (ui_clk_sync_rst) + ui_clk_syn_rst_delayed <= 1'b1; + else begin + ui_clk_syn_rst_delayed <= delay_cnt != 0; + end + end + + assign afifo_rst_1 = ui_clk_syn_rst_delayed; + assign mem_ui_clk_sync_rst = ui_clk_syn_rst_delayed; + + assign ui_clk = mig_ddr3_ui_clk; + always @(posedge ui_clk) begin + afifo_ui_rst_r <= afifo_rst_1; + afifo_ui_rst_r_r <= afifo_ui_rst_r; + end + + assign ui_clk_sync_rst = noc_axi4_bridge_rst; + assign afifo_rst_2 = afifo_ui_rst_r_r | ui_clk_sync_rst; + + // ------------------------------------------------------------------------------- + // Instances + // ------------------------------------------------------------------------------- + noc_bidir_afifo mig_afifo ( + .clk_1 (chipset_clk), + .rst_1 (afifo_rst_1), + + .clk_2 (mig_ddr3_ui_clk), + .rst_2 (afifo_rst_2), + + // CPU --> MIG + .flit_in_val_1 (mem_flit_in_val), + .flit_in_data_1 (mem_flit_in_data), + .flit_in_rdy_1 (mem_flit_in_rdy), + + .flit_out_val_2 (fifo_trans_val), + .flit_out_data_2 (fifo_trans_data), + .flit_out_rdy_2 (fifo_trans_rdy), + + // MIG --> CPU + .flit_in_val_2 (trans_fifo_val), + .flit_in_data_2 (trans_fifo_data), + .flit_in_rdy_2 (trans_fifo_rdy), + + .flit_out_val_1 (mem_flit_out_val), + .flit_out_data_1 (mem_flit_out_data), + .flit_out_rdy_1 (mem_flit_out_rdy) + ); + + noc_axi4_bridge noc_axi4_bridge ( + .clk (mig_ddr3_ui_clk), + .rst_n (~noc_axi4_bridge_rst), + .uart_boot_en (uart_boot_en), + .phy_init_done (noc_axi4_bridge_init_done), + + .src_bridge_vr_noc2_val (fifo_trans_val), + .src_bridge_vr_noc2_dat (fifo_trans_data), + .src_bridge_vr_noc2_rdy (fifo_trans_rdy), + + .bridge_dst_vr_noc3_val (trans_fifo_val), + .bridge_dst_vr_noc3_dat (trans_fifo_data), + .bridge_dst_vr_noc3_rdy (trans_fifo_rdy), + + .m_axi_awid (ddr3_axi_awid), + .m_axi_awaddr (ddr3_axi_awaddr), + .m_axi_awlen (ddr3_axi_awlen), + .m_axi_awsize (ddr3_axi_awsize), + .m_axi_awburst (ddr3_axi_awburst), + .m_axi_awlock (ddr3_axi_awlock), + .m_axi_awcache (ddr3_axi_awcache), + .m_axi_awprot (ddr3_axi_awprot), + .m_axi_awqos (ddr3_axi_awqos), + .m_axi_awregion (m_axi_awregion), // not used + .m_axi_awuser (m_axi_awuser), // not used + .m_axi_awvalid (ddr3_axi_awvalid), + .m_axi_awready (ddr3_axi_awready), + + .m_axi_wid (m_axi_wid), // not used + .m_axi_wdata (ddr3_axi_wdata), + .m_axi_wstrb (ddr3_axi_wstrb), + .m_axi_wlast (ddr3_axi_wlast), + .m_axi_wuser (m_axi_wuser), // not used + .m_axi_wvalid (ddr3_axi_wvalid), + .m_axi_wready (ddr3_axi_wready), + + .m_axi_bid (ddr3_axi_bid), + .m_axi_bresp (ddr3_axi_bresp), + .m_axi_buser (m_axi_buser), // not used + .m_axi_bvalid (ddr3_axi_bvalid), + .m_axi_bready (ddr3_axi_bready), + + .m_axi_arid (ddr3_axi_arid), + .m_axi_araddr (ddr3_axi_araddr), + .m_axi_arlen (ddr3_axi_arlen), + .m_axi_arsize (ddr3_axi_arsize), + .m_axi_arburst (ddr3_axi_arburst), + .m_axi_arlock (ddr3_axi_arlock), + .m_axi_arcache (ddr3_axi_arcache), + .m_axi_arprot (ddr3_axi_arprot), + .m_axi_arqos (ddr3_axi_arqos), + .m_axi_arregion (m_axi_arregion), // not used + .m_axi_aruser (m_axi_aruser), // not used + .m_axi_arvalid (ddr3_axi_arvalid), + .m_axi_arready (ddr3_axi_arready), + + .m_axi_rid (ddr3_axi_rid), + .m_axi_rdata (ddr3_axi_rdata), + .m_axi_rresp (ddr3_axi_rresp), + .m_axi_rlast (ddr3_axi_rlast), + .m_axi_ruser (m_axi_ruser), // not used + .m_axi_rvalid (ddr3_axi_rvalid), + .m_axi_rready (ddr3_axi_rready) + + ); + + `ifndef POLARA_GEN2_CHIPSETSE + gen2_polara_fpga gen2_polara_fpga_i( + // AXI Interface for NOC/Master + .ddr3_axi_araddr(ddr3_axi_araddr), + .ddr3_axi_arburst(ddr3_axi_arburst), + .ddr3_axi_arcache(ddr3_axi_arcache), + .ddr3_axi_arid(ddr3_axi_arid), + .ddr3_axi_arlen(ddr3_axi_arlen), + .ddr3_axi_arlock(ddr3_axi_arlock), + .ddr3_axi_arprot(ddr3_axi_arprot), + .ddr3_axi_arqos(ddr3_axi_arqos), + .ddr3_axi_arready(ddr3_axi_arready), + .ddr3_axi_arsize(ddr3_axi_arsize), + .ddr3_axi_arvalid(ddr3_axi_arvalid), + .ddr3_axi_awaddr(ddr3_axi_awaddr), + .ddr3_axi_awburst(ddr3_axi_awburst), + .ddr3_axi_awcache(ddr3_axi_awcache), + .ddr3_axi_awid(ddr3_axi_awid), + .ddr3_axi_awlen(ddr3_axi_awlen), + .ddr3_axi_awlock(ddr3_axi_awlock), + .ddr3_axi_awprot(ddr3_axi_awprot), + .ddr3_axi_awqos(ddr3_axi_awqos), + .ddr3_axi_awready(ddr3_axi_awready), + .ddr3_axi_awsize(ddr3_axi_awsize), + .ddr3_axi_awvalid(ddr3_axi_awvalid), + .ddr3_axi_bid(ddr3_axi_bid), + .ddr3_axi_bready(ddr3_axi_bready), + .ddr3_axi_bresp(ddr3_axi_bresp), + .ddr3_axi_bvalid(ddr3_axi_bvalid), + .ddr3_axi_rdata(ddr3_axi_rdata), + .ddr3_axi_rid(ddr3_axi_rid), + .ddr3_axi_rlast(ddr3_axi_rlast), + .ddr3_axi_rready(ddr3_axi_rready), + .ddr3_axi_rresp(ddr3_axi_rresp), + .ddr3_axi_rvalid(ddr3_axi_rvalid), + .ddr3_axi_wdata(ddr3_axi_wdata), + .ddr3_axi_wlast(ddr3_axi_wlast), + .ddr3_axi_wready(ddr3_axi_wready), + .ddr3_axi_wstrb(ddr3_axi_wstrb), + .ddr3_axi_wvalid(ddr3_axi_wvalid), + // DDR3 Physical Interface + .ddr3_sdram_addr(ddr3_sdram_addr), + .ddr3_sdram_ba(ddr3_sdram_ba), + .ddr3_sdram_cas_n(ddr3_sdram_cas_n), + .ddr3_sdram_ck_n(ddr3_sdram_ck_n), + .ddr3_sdram_ck_p(ddr3_sdram_ck_p), + .ddr3_sdram_cke(ddr3_sdram_cke), + .ddr3_sdram_cs_n(ddr3_sdram_cs_n), + .ddr3_sdram_dm(ddr3_sdram_dm), + .ddr3_sdram_dq(ddr3_sdram_dq), + .ddr3_sdram_dqs_n(ddr3_sdram_dqs_n), + .ddr3_sdram_dqs_p(ddr3_sdram_dqs_p), + .ddr3_sdram_odt(ddr3_sdram_odt), + .ddr3_sdram_ras_n(ddr3_sdram_ras_n), + .ddr3_sdram_reset_n(ddr3_sdram_reset_n), + .ddr3_sdram_we_n(ddr3_sdram_we_n), + // DDR3 memory ready + .mig_ddr3_init_calib_complete(noc_axi4_bridge_init_done), + // Input Clock for MIG + // Xilinx recommends an external clock as the input clock (low jitter) + .mig_ddr3_sys_diff_clock_clk_n(mig_ddr3_sys_diff_clock_clk_n), + .mig_ddr3_sys_diff_clock_clk_p(mig_ddr3_sys_diff_clock_clk_p), + // Asynchronous reset for the MIG's sys_rst_n + // also used as reset for the AXI bus (synced with ui_clk) + .mig_ddr3_sys_rst_n(sys_rst_n), + // MIG generated ui_clk and synchronized reset + .mig_ddr3_ui_clk(mig_ddr3_ui_clk), + .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst) + ); + `else // !`ifndef POLARA_GEN2_CHIPSETSE + gen2_polara_fpga_se_clk gen2_polara_fpga_se_clk_i + (.ddr3_axi_araddr(ddr3_axi_araddr), + .ddr3_axi_arburst(ddr3_axi_arburst), + .ddr3_axi_arcache(ddr3_axi_arcache), + .ddr3_axi_arid(ddr3_axi_arid), + .ddr3_axi_arlen(ddr3_axi_arlen), + .ddr3_axi_arlock(ddr3_axi_arlock), + .ddr3_axi_arprot(ddr3_axi_arprot), + .ddr3_axi_arqos(ddr3_axi_arqos), + .ddr3_axi_arready(ddr3_axi_arready), + .ddr3_axi_arsize(ddr3_axi_arsize), + .ddr3_axi_arvalid(ddr3_axi_arvalid), + .ddr3_axi_awaddr(ddr3_axi_awaddr), + .ddr3_axi_awburst(ddr3_axi_awburst), + .ddr3_axi_awcache(ddr3_axi_awcache), + .ddr3_axi_awid(ddr3_axi_awid), + .ddr3_axi_awlen(ddr3_axi_awlen), + .ddr3_axi_awlock(ddr3_axi_awlock), + .ddr3_axi_awprot(ddr3_axi_awprot), + .ddr3_axi_awqos(ddr3_axi_awqos), + .ddr3_axi_awready(ddr3_axi_awready), + .ddr3_axi_awsize(ddr3_axi_awsize), + .ddr3_axi_awvalid(ddr3_axi_awvalid), + .ddr3_axi_bid(ddr3_axi_bid), + .ddr3_axi_bready(ddr3_axi_bready), + .ddr3_axi_bresp(ddr3_axi_bresp), + .ddr3_axi_bvalid(ddr3_axi_bvalid), + .ddr3_axi_rdata(ddr3_axi_rdata), + .ddr3_axi_rid(ddr3_axi_rid), + .ddr3_axi_rlast(ddr3_axi_rlast), + .ddr3_axi_rready(ddr3_axi_rready), + .ddr3_axi_rresp(ddr3_axi_rresp), + .ddr3_axi_rvalid(ddr3_axi_rvalid), + .ddr3_axi_wdata(ddr3_axi_wdata), + .ddr3_axi_wlast(ddr3_axi_wlast), + .ddr3_axi_wready(ddr3_axi_wready), + .ddr3_axi_wstrb(ddr3_axi_wstrb), + .ddr3_axi_wvalid(ddr3_axi_wvalid), + .ddr3_sdram_addr(ddr3_sdram_addr), + .ddr3_sdram_ba(ddr3_sdram_ba), + .ddr3_sdram_cas_n(ddr3_sdram_cas_n), + .ddr3_sdram_ck_n(ddr3_sdram_ck_n), + .ddr3_sdram_ck_p(ddr3_sdram_ck_p), + .ddr3_sdram_cke(ddr3_sdram_cke), + .ddr3_sdram_cs_n(ddr3_sdram_cs_n), + .ddr3_sdram_dm(ddr3_sdram_dm), + .ddr3_sdram_dq(ddr3_sdram_dq), + .ddr3_sdram_dqs_n(ddr3_sdram_dqs_n), + .ddr3_sdram_dqs_p(ddr3_sdram_dqs_p), + .ddr3_sdram_odt(ddr3_sdram_odt), + .ddr3_sdram_ras_n(ddr3_sdram_ras_n), + .ddr3_sdram_reset_n(ddr3_sdram_reset_n), + .ddr3_sdram_we_n(ddr3_sdram_we_n), + .mig_ddr3_init_calib_complete(noc_axi4_bridge_init_done), + .mig_ddr3_sys_rst_n(sys_rst_n), + .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), + .mig_ddr3_ui_clk(mig_ddr3_ui_clk), + .mig_ddr3_ui_clk_sync_rst(noc_axi4_bridge_rst), + .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), + .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o) + ); + + // Route polara_gen2chipset_bus signals + assign chip_rst_n = polara_gen2chipset_bus_o[0]; + assign chip_async_mux = polara_gen2chipset_bus_o[1]; + assign chip_clk_en = polara_gen2chipset_bus_o[2]; + assign chip_clk_mux_sel = polara_gen2chipset_bus_o[3]; + + assign fll_rst_n = polara_gen2chipset_bus_o[4]; + assign fll_bypass = polara_gen2chipset_bus_o[5]; + assign fll_opmode = polara_gen2chipset_bus_o[6]; + assign fll_cfg_req = polara_gen2chipset_bus_o[7]; + + assign fll_range[3:0] = polara_gen2chipset_bus_o[11:8]; + + assign polara_gen2chipset_bus_i[0] = fll_lock; + assign polara_gen2chipset_bus_i[1] = fll_clkdiv; + + + + `endif // !`ifndef POLARA_GEN2_CHIPSETSE + + + +endmodule diff --git a/piton/design/chipset/mc/rtl/u280_polara_top.sv b/piton/design/chipset/mc/rtl/u280_polara_top.sv new file mode 100644 index 000000000..1652b9060 --- /dev/null +++ b/piton/design/chipset/mc/rtl/u280_polara_top.sv @@ -0,0 +1,302 @@ + +`include "mc_define.h" + +`include "noc_axi4_bridge_define.vh" + +module u280_polara_top ( + + input logic pcie_refclk_clk_n , + input logic pcie_refclk_clk_p , + input logic pcie_perstn , + input logic [15:0] pci_express_x16_rxn , + input logic [15:0] pci_express_x16_rxp , + output logic [15:0] pci_express_x16_txn , + output logic [15:0] pci_express_x16_txp , + input logic resetn , + + output logic c0_ddr4_act_n, + output logic [16:0] c0_ddr4_adr, + output logic [1:0] c0_ddr4_ba, + output logic [1:0] c0_ddr4_bg, + output logic [0:0] c0_ddr4_ck_c, + output logic [0:0] c0_ddr4_ck_t, + output logic [0:0] c0_ddr4_cke, + output logic [0:0] c0_ddr4_cs_n, + inout wire [71:0] c0_ddr4_dq, + inout wire [17:0] c0_ddr4_dqs_c, + inout wire [17:0] c0_ddr4_dqs_t, + output logic [0:0] c0_ddr4_odt, + output logic c0_ddr4_par, + output logic c0_ddr4_reset_n, + output logic c0_ddr4_ui_clk_sync_rst, + + // Reference clock + input logic c0_sysclk_clk_n, + input logic c0_sysclk_clk_p, + // input mc_clk , + // input mc_rstn , + output logic chip_rstn , + input logic chipset_clk , + input logic chipset_rstn , + output logic c0_init_calib_complete, + + input logic [`NOC_DATA_WIDTH-1:0] mem_flit_in_data , + input logic mem_flit_in_val , + output logic mem_flit_in_rdy , + + output logic [`NOC_DATA_WIDTH-1:0] mem_flit_out_data , + output logic mem_flit_out_val , + input logic mem_flit_out_rdy +); + + + logic mc_rst; + logic mc_clk; + + + logic trans_fifo_val; + logic [`NOC_DATA_WIDTH-1:0] trans_fifo_data; + logic trans_fifo_rdy; + + logic fifo_trans_val; + logic [`NOC_DATA_WIDTH-1:0] fifo_trans_data; + logic fifo_trans_rdy; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_awid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_awaddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_awlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_awsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_awburst; + logic m_axi_awlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_awcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_awprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_awqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_awregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_awuser; + logic m_axi_awvalid; + logic m_axi_awready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_wid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_wdata; + logic [`AXI4_STRB_WIDTH -1:0] m_axi_wstrb; + logic m_axi_wlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_wuser; + logic m_axi_wvalid; + logic m_axi_wready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_arid; + logic [`AXI4_ADDR_WIDTH -1:0] m_axi_araddr; + logic [`AXI4_LEN_WIDTH -1:0] m_axi_arlen; + logic [`AXI4_SIZE_WIDTH -1:0] m_axi_arsize; + logic [`AXI4_BURST_WIDTH -1:0] m_axi_arburst; + logic m_axi_arlock; + logic [`AXI4_CACHE_WIDTH -1:0] m_axi_arcache; + logic [`AXI4_PROT_WIDTH -1:0] m_axi_arprot; + logic [`AXI4_QOS_WIDTH -1:0] m_axi_arqos; + logic [`AXI4_REGION_WIDTH -1:0] m_axi_arregion; + logic [`AXI4_USER_WIDTH -1:0] m_axi_aruser; + logic m_axi_arvalid; + logic m_axi_arready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_rid; + logic [`AXI4_DATA_WIDTH -1:0] m_axi_rdata; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_rresp; + logic m_axi_rlast; + logic [`AXI4_USER_WIDTH -1:0] m_axi_ruser; + logic m_axi_rvalid; + logic m_axi_rready; + + logic [`AXI4_ID_WIDTH -1:0] m_axi_bid; + logic [`AXI4_RESP_WIDTH -1:0] m_axi_bresp; + logic [`AXI4_USER_WIDTH -1:0] m_axi_buser; + logic m_axi_bvalid; + logic m_axi_bready; + + noc_bidir_afifo mig_afifo ( + .clk_1 ( chipset_clk ), + .rst_1 ( ~chipset_rstn ), + + .clk_2 ( mc_clk ), + .rst_2 ( mc_rst ), + + // CPU --> MIG + .flit_in_val_1 ( mem_flit_in_val ), + .flit_in_data_1 ( mem_flit_in_data ), + .flit_in_rdy_1 ( mem_flit_in_rdy ), + + .flit_out_val_2 ( fifo_trans_val ), + .flit_out_data_2 ( fifo_trans_data ), + .flit_out_rdy_2 ( fifo_trans_rdy ), + + // MIG --> CPU + .flit_in_val_2 ( trans_fifo_val ), + .flit_in_data_2 ( trans_fifo_data ), + .flit_in_rdy_2 ( trans_fifo_rdy ), + + .flit_out_val_1 ( mem_flit_out_val ), + .flit_out_data_1 ( mem_flit_out_data ), + .flit_out_rdy_1 ( mem_flit_out_rdy ) + ); + + + noc_axi4_bridge noc_axi4_bridge ( + .clk ( mc_clk ), + .rst_n ( ~mc_rst ), + .uart_boot_en ( 1'b0 ), + .phy_init_done ( c0_init_calib_complete ), + + .src_bridge_vr_noc2_val ( fifo_trans_val ), + .src_bridge_vr_noc2_dat ( fifo_trans_data ), + .src_bridge_vr_noc2_rdy ( fifo_trans_rdy ), + + .bridge_dst_vr_noc3_val ( trans_fifo_val ), + .bridge_dst_vr_noc3_dat ( trans_fifo_data ), + .bridge_dst_vr_noc3_rdy ( trans_fifo_rdy ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + + .m_axi_wid ( m_axi_wid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_buser ( m_axi_buser ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + + .m_axi_rid ( m_axi_rid), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + + ); + + polara_fpga polara_i ( + + .c0_sysclk_clk_p ( c0_sysclk_clk_p ), + .c0_sysclk_clk_n ( c0_sysclk_clk_n ), + .c0_ddr4_ui_clk ( mc_clk ), + .c0_ddr4_ui_clk_sync_rst ( mc_rst ), + .c0_init_calib_complete ( c0_init_calib_complete ), + + // DDR4 physicall interface + .c0_ddr4_act_n ( c0_ddr4_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( c0_ddr4_adr ), + .c0_ddr4_ba ( c0_ddr4_ba ), + .c0_ddr4_bg ( c0_ddr4_bg ), // bank group address + .c0_ddr4_ck_t ( c0_ddr4_ck_t ), + .c0_ddr4_ck_c ( c0_ddr4_ck_c ), + .c0_ddr4_cke ( c0_ddr4_cke ), + .c0_ddr4_cs_n ( c0_ddr4_cs_n ), + .c0_ddr4_dq ( c0_ddr4_dq ), + .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .c0_ddr4_odt ( c0_ddr4_odt ), + .c0_ddr4_par ( c0_ddr4_par ), // output logic c0_ddr4_parity + .c0_ddr4_reset_n ( c0_ddr4_reset_n ), + + // DDR4 control interface, not used, grounded + .c0_ddr4_s_axi_ctrl_awvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_awvalid + .c0_ddr4_s_axi_ctrl_awready( ), // output logic c0_ddr4_s_axi_ctrl_awready + .c0_ddr4_s_axi_ctrl_awaddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_awaddr + .c0_ddr4_s_axi_ctrl_wvalid (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_wvalid + .c0_ddr4_s_axi_ctrl_wready ( ), // output logic c0_ddr4_s_axi_ctrl_wready + .c0_ddr4_s_axi_ctrl_wdata (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_wdata + .c0_ddr4_s_axi_ctrl_bvalid ( ), // output logic c0_ddr4_s_axi_ctrl_bvalid + .c0_ddr4_s_axi_ctrl_bready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_bready + .c0_ddr4_s_axi_ctrl_bresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_bresp + .c0_ddr4_s_axi_ctrl_arvalid(1'b0 ), // input logic c0_ddr4_s_axi_ctrl_arvalid + .c0_ddr4_s_axi_ctrl_arready( ), // output logic c0_ddr4_s_axi_ctrl_arready + .c0_ddr4_s_axi_ctrl_araddr (32'b0 ), // input logic [31 : 0] c0_ddr4_s_axi_ctrl_araddr + .c0_ddr4_s_axi_ctrl_rvalid ( ), // output logic c0_ddr4_s_axi_ctrl_rvalid + .c0_ddr4_s_axi_ctrl_rready (1'b0 ), // input logic c0_ddr4_s_axi_ctrl_rready + .c0_ddr4_s_axi_ctrl_rdata ( ), // output logic [31 : 0] c0_ddr4_s_axi_ctrl_rdata + .c0_ddr4_s_axi_ctrl_rresp ( ), // output logic [1 : 0] c0_ddr4_s_axi_ctrl_rresp + + .chip_rstn ( chip_rstn ), + + // AXI4 Memory Interface + .c0_ddr4_s_axi_awid ( m_axi_awid), // input logic [15 : 0] c0_ddr4_s_axi_awid + .c0_ddr4_s_axi_awaddr ( m_axi_awaddr), // input logic [34 : 0] c0_ddr4_s_axi_awaddr + .c0_ddr4_s_axi_awlen ( m_axi_awlen), // input logic [7 : 0] c0_ddr4_s_axi_awlen + .c0_ddr4_s_axi_awsize ( m_axi_awsize), // input logic [2 : 0] c0_ddr4_s_axi_awsize + .c0_ddr4_s_axi_awburst ( m_axi_awburst), // input logic [1 : 0] c0_ddr4_s_axi_awburst + .c0_ddr4_s_axi_awlock ( m_axi_awlock), // input logic [0 : 0] c0_ddr4_s_axi_awlock + .c0_ddr4_s_axi_awcache ( m_axi_awcache), // input logic [3 : 0] c0_ddr4_s_axi_awcache + .c0_ddr4_s_axi_awprot ( m_axi_awprot), // input logic [2 : 0] c0_ddr4_s_axi_awprot + .c0_ddr4_s_axi_awqos ( m_axi_awqos), // input logic [3 : 0] c0_ddr4_s_axi_awqos + .c0_ddr4_s_axi_awvalid ( m_axi_awvalid), // input logic c0_ddr4_s_axi_awvalid + .c0_ddr4_s_axi_awready ( m_axi_awready), // output logic c0_ddr4_s_axi_awready + .c0_ddr4_s_axi_wdata ( m_axi_wdata), // input logic [511 : 0] c0_ddr4_s_axi_wdata + .c0_ddr4_s_axi_wstrb ( m_axi_wstrb), // input logic [63 : 0] c0_ddr4_s_axi_wstrb + .c0_ddr4_s_axi_wlast ( m_axi_wlast), // input logic c0_ddr4_s_axi_wlast + .c0_ddr4_s_axi_wvalid ( m_axi_wvalid), // input logic c0_ddr4_s_axi_wvalid + .c0_ddr4_s_axi_wready ( m_axi_wready), // output logic c0_ddr4_s_axi_wready + .c0_ddr4_s_axi_bready ( m_axi_bready), // input logic c0_ddr4_s_axi_bready + .c0_ddr4_s_axi_bid ( m_axi_bid), // output logic [15 : 0] c0_ddr4_s_axi_bid + .c0_ddr4_s_axi_bresp ( m_axi_bresp), // output logic [1 : 0] c0_ddr4_s_axi_bresp + .c0_ddr4_s_axi_bvalid ( m_axi_bvalid), // output logic c0_ddr4_s_axi_bvalid + .c0_ddr4_s_axi_arid ( m_axi_arid), // input logic [15 : 0] c0_ddr4_s_axi_arid + .c0_ddr4_s_axi_araddr ( m_axi_araddr), // input logic [34 : 0] c0_ddr4_s_axi_araddr + .c0_ddr4_s_axi_arlen ( m_axi_arlen), // input logic [7 : 0] c0_ddr4_s_axi_arlen + .c0_ddr4_s_axi_arsize ( m_axi_arsize), // input logic [2 : 0] c0_ddr4_s_axi_arsize + .c0_ddr4_s_axi_arburst ( m_axi_arburst), // input logic [1 : 0] c0_ddr4_s_axi_arburst + .c0_ddr4_s_axi_arlock ( m_axi_arlock), // input logic [0 : 0] c0_ddr4_s_axi_arlock + .c0_ddr4_s_axi_arcache ( m_axi_arcache), // input logic [3 : 0] c0_ddr4_s_axi_arcache + .c0_ddr4_s_axi_arprot ( m_axi_arprot), // input logic [2 : 0] c0_ddr4_s_axi_arprot + .c0_ddr4_s_axi_arqos ( m_axi_arqos), // input logic [3 : 0] c0_ddr4_s_axi_arqos + .c0_ddr4_s_axi_arvalid ( m_axi_arvalid), // input logic c0_ddr4_s_axi_arvalid + .c0_ddr4_s_axi_arready ( m_axi_arready), // output logic c0_ddr4_s_axi_arready + .c0_ddr4_s_axi_rready ( m_axi_rready), // input logic c0_ddr4_s_axi_rready + .c0_ddr4_s_axi_rlast ( m_axi_rlast), // output logic c0_ddr4_s_axi_rlast + .c0_ddr4_s_axi_rvalid ( m_axi_rvalid), // output logic c0_ddr4_s_axi_rvalid + .c0_ddr4_s_axi_rresp ( m_axi_rresp), // output logic [1 : 0] c0_ddr4_s_axi_rresp + .c0_ddr4_s_axi_rid ( m_axi_rid), // output logic [15 : 0] c0_ddr4_s_axi_rid + .c0_ddr4_s_axi_rdata ( m_axi_rdata), // output logic [511 : 0] c0_ddr4_s_axi_rdata + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn) + ); + +endmodule + diff --git a/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci b/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci index 506fc8d7c..8a128e4f8 100644 --- a/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci +++ b/piton/design/chipset/mc/xilinx/genesys2/ip_cores/mig_7series_0/mig_7series_0.xci @@ -7,8 +7,1215 @@ mig_7series_0 - + + 0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 32 32 32 @@ -1162,33 +2369,389 @@ Custom mig_a.prj kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 2 + 1 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci index e46abc50c..69c8d2150 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_cache_bram/sd_cache_bram.xci @@ -7,9 +7,89 @@ sd_cache_bram - + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0 + 0.0 + 0 9 9 1 @@ -60,6 +140,8 @@ 1 512 512 + 1 + 1 64 64 0 @@ -126,6 +208,8 @@ 8kx2 false false + 1 + 1 64 64 false @@ -154,28 +238,64 @@ false Stand_Alone kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 5 + 4 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -185,6 +305,14 @@ + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci index 2a58d39f4..48dd33a64 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_ctrl_fifo/sd_ctrl_fifo.xci @@ -7,13 +7,129 @@ sd_ctrl_fifo - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,28 +501,58 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -421,6 +567,14 @@ + + + diff --git a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci index eeae03d3d..7d1474350 100644 --- a/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci +++ b/piton/design/chipset/noc_sd_bridge/xilinx/genesys2/ip_cores/sd_data_fifo/sd_data_fifo.xci @@ -7,13 +7,129 @@ sd_data_fifo - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,28 +501,58 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -421,6 +567,14 @@ + + + diff --git a/piton/design/chipset/oled/rtl/oled_wrapper.v b/piton/design/chipset/oled/rtl/oled_wrapper.v index 879ec3993..dd5c9943e 100644 --- a/piton/design/chipset/oled/rtl/oled_wrapper.v +++ b/piton/design/chipset/oled/rtl/oled_wrapper.v @@ -152,6 +152,7 @@ assign btnu_pulse = btnu & ~btnu_r; always @(posedge sys_clk) begin disp_string <= `OLED_STRING; + //disp_string <= "0123456789012345678901234567890123456789012345678901234567891234"; end generate begin @@ -172,4 +173,4 @@ generate begin end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/piton/design/chipset/rtl/chipset.v b/piton/design/chipset/rtl/chipset.v index 840b49d23..182a7fee1 100644 --- a/piton/design/chipset/rtl/chipset.v +++ b/piton/design/chipset/rtl/chipset.v @@ -82,7 +82,9 @@ // PITON_NOC_POWER_CHIPSET_TEST This indicates to use a completely different // chipset that just sends dummy network packets // into the chip for testing NoC power - +// POLARA_GEN2_CHIPSET Uses specific memory controller for the chipset being implemented +// on a genesys2 board for the Polara project. +// POLARA_GEN2_CHIPSETSE Uses a single ended clock for the MIG instead of differential. module chipset( @@ -94,7 +96,18 @@ module chipset( `ifdef F1_BOARD input sys_clk, `else +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , // Oscillator clock +`endif //ifdef ALVEO_BOARD `ifdef PITON_CHIPSET_CLKS_GEN `ifdef PITON_CHIPSET_DIFF_CLK input clk_osc_p, @@ -154,11 +167,13 @@ module chipset( `endif // Piton ready input +`ifndef POLARA_GEN2_CHIPSETSE `ifndef PITON_BOARD input piton_ready_n, input piton_prsnt_n, output chipset_prsnt_n, `endif // PITON_BOARD +`endif // POLARA_GEN2_CHIPSETSE // There are actually 3 options for how to // communicate to the chip: directly without a @@ -223,6 +238,7 @@ module chipset( `endif // endif PITON_NO_CHIP_BRIDGE PITONSYS_INC_PASSTHRU // DRAM and I/O interfaces +`ifndef POLARA_LOOPBACK // No need for DDR for Polara loopback tests `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 // Generalized interface for any FPGA board we support. @@ -249,11 +265,11 @@ module chipset( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -319,6 +335,7 @@ module chipset( `endif // ifndef F1_BOARD `endif //`ifdef PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC +`endif // `ifndef POLARA_LOOPBACK `ifdef PITONSYS_IOCTRL @@ -365,6 +382,39 @@ module chipset( `endif // endif PITONSYS_IOCTRL +// Polara Board specific I/Os +`ifdef POLARA_GEN2_CHIPSETSE + output wire chip_async_mux, + output wire chip_clk_en, + output wire chip_clk_mux_sel, + output wire chip_rst_n, + output wire fll_rst_n, + output wire fll_bypass, + input wire fll_clkdiv, + input wire fll_lock, + output wire fll_cfg_req, + output wire fll_opmode, + output wire [3:0] fll_range, + + output wire dbg0, + output wire dbg1, + output wire dbg2, + output wire dbg3, + output wire dbg4, + output wire dbg5, + output wire dbg6, + output wire dbg7, + output wire dbg8, + output wire dbg9, + output wire dbg10, + output wire dbg11, + output wire dbg12, + output wire dbg13, + output wire dbg14, + output wire dbg15, + +`endif + // Piton Board specific I/Os `ifdef PITON_BOARD output [1:0] sma_clk_out_p, @@ -467,13 +517,13 @@ module chipset( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, - `elsif XUPP3R_BOARD + `elsif XUPP3R_OR_ALVEO // no switches :( `else input [7:0] sw, `endif - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO output [3:0] leds `else output [7:0] leds @@ -497,6 +547,13 @@ module chipset( wire mc_clk; `endif // endif PITON_CHIPSET_CLKS_GEN +`ifdef POLARA_GEN2_CHIPSETSE + wire io_clk_wire; + wire io_clk_wire_int; + wire io_clk_not_wire_int; + wire io_clk_wire_phase_sel; +`endif + `ifdef PITON_BOARD // Internal generated clocks wire core_ref_clk_inter; @@ -643,7 +700,6 @@ wire sd_clk_out_internal; // the packet filter to peripherals flags invalid accesses wire invalid_access; - ////////////////////// // Sequential Logic // ////////////////////// @@ -669,11 +725,15 @@ end fpga_intf_rdy_noc3 ? 1'b1 : passthru_fifo_init_complete; end `endif // PITON_BOARD - + ///////////////////////// // Combinational Logic // ///////////////////////// - +`ifdef POLARA_GEN2_CHIPSETSE + assign io_clk_wire_phase_sel = sw[5]; + assign io_clk_wire = io_clk_wire_phase_sel ? io_clk_not_wire_int : io_clk_wire_int; +`endif + `ifndef PITON_BOARD `ifndef PITONSYS_INC_PASSTHRU assign io_clk_loopback = io_clk; @@ -684,7 +744,12 @@ end // this chipset clocks. This means everything is synchronous // to the same clock assign core_ref_clk = chipset_clk; - assign io_clk = chipset_clk; + `ifndef POLARA_GEN2_CHIPSETSE + assign io_clk = chipset_clk; + `else + assign io_clk = io_clk_wire; + `endif + `endif // PITON_CLKS_CHIPSET `endif // PITON_BOARD @@ -703,8 +768,12 @@ begin `else `ifdef PITONSYS_UART_RESET chipset_rst_n = rst_n_rect & clk_locked & (~piton_prsnt_n) & uart_rst_out_n; +`else +`ifdef POLARA_GEN2_CHIPSET + chipset_rst_n = rst_n_rect & clk_locked; `else chipset_rst_n = rst_n_rect & clk_locked & (~piton_prsnt_n); +`endif // POLARA_GEN2_CHIPSET `endif // PITONSYS_UART_RESET `endif // PITON_BOARD @@ -731,7 +800,7 @@ end `ifdef VCU118_BOARD assign uart_boot_en = sw[0]; assign uart_timeout_en = sw[1]; - `elsif XUPP3R_BOARD + `elsif XUPP3R_OR_ALVEO assign uart_boot_en = 1'b1; assign uart_timeout_en = 1'b0; `else @@ -789,14 +858,57 @@ end assign leds[1] = init_calib_complete; assign leds[2] = processor_offchip_noc2_valid; assign leds[3] = offchip_processor_noc3_valid; +`elsif ALVEO_BOARD + assign leds[0] = 1'b1; + assign leds[1] = init_calib_complete; + assign leds[2] = processor_offchip_noc2_valid; + assign leds[3] = offchip_processor_noc3_valid; +`elsif POLARA_GEN2_CHIPSET + assign dbg0 = fll_clkdiv; + assign dbg1 = chipset_clk; + assign dbg2 = chipset_clk; + assign dbg3 = intf_chip_credit_back[0]; + assign dbg4 = intf_chip_credit_back[1]; + assign dbg5 = intf_chip_credit_back[2]; + assign dbg6 = chip_intf_channel[0]; + assign dbg7 = chip_intf_channel[1]; + assign dbg8 = intf_chip_channel[0]; + assign dbg9 = intf_chip_channel[1]; + assign dbg10 = chip_intf_credit_back[0]; + assign dbg11 = chip_intf_credit_back[1]; + assign dbg12 = chip_intf_credit_back[2]; + assign dbg13 = chip_intf_data[0]; + assign dbg14 = chip_intf_data[1]; + assign dbg15 = chip_intf_data[2]; + + assign leds[0] = clk_locked; + assign leds[1] = fll_lock; + assign leds[2] = test_start; + assign leds[3] = init_calib_complete; + assign leds[4] = chipset_rst_n_ff; + assign leds[5] = chipset_rst_n_ff; + assign leds[6] = rst_n; + `ifdef PITONSYS_IOCTRL + `ifdef PITONSYS_UART + `ifdef PITONSYS_UART_BOOT + assign leds[7] = uart_boot_en; + `else // ifndef PITONSYS_UART_BOOT + assign leds[7] = 1'b0; + `endif // endif PITONSYS_UART_BOOT + `else // ifndef PITONSYS_UART + assign leds[7] = 1'b0; + `endif // endif PITONSYS_UART + `else // ifndef PITONSYS_IOCTRL + assign leds[7] = 1'b0; + `endif // endif PITONSYS_IOCTRL `else // PITON_BOARD assign leds[0] = clk_locked; assign leds[1] = ~piton_ready_n; assign leds[2] = init_calib_complete; - assign leds[3] = processor_offchip_noc2_valid; - assign leds[4] = offchip_processor_noc3_valid; - assign leds[5] = 1'b0; - assign leds[6] = invalid_access; + assign leds[3] = chipset_rst_n_ff; + assign leds[4] = piton_prsnt_n; + assign leds[5] = test_start; + assign leds[6] = chip_rst_n; `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART `ifdef PITONSYS_UART_BOOT @@ -849,12 +961,17 @@ end .clk_in1(clk_osc), `endif // endif PITON_CHIPSET_DIFF_CLK + `ifdef POLARA_GEN2_CHIPSETSE + .io_clk(io_clk_wire_int), + .io_clk_not(io_clk_not_wire_int), + `endif + .reset(1'b0), .locked(clk_locked), - + // Main chipset clock .chipset_clk(chipset_clk) - + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 // Memory controller clock @@ -999,6 +1116,7 @@ fpga_bridge( .fpga_out_clk (chipset_clk ), .fpga_in_clk (chipset_clk ), + `ifndef POLARA_GEN2_CHIPSETSE `ifdef PITONSYS_INC_PASSTHRU .intf_out_clk (chipset_passthru_clk ), .intf_in_clk (passthru_chipset_clk ), @@ -1006,6 +1124,11 @@ fpga_bridge( .intf_out_clk (io_clk_loopback ), .intf_in_clk (io_clk_loopback ), `endif // endif PITONSYS_INC_PASSTHRU + `endif // endif POLARA_GEN2_CHIPSETSE + `ifdef POLARA_GEN2_CHIPSETSE + .intf_out_clk (io_clk_wire_int ), + .intf_in_clk (io_clk_wire_int ), + `endif .fpga_intf_data_noc1(fpga_intf_data_noc1), .fpga_intf_data_noc2(fpga_intf_data_noc2), @@ -1204,27 +1327,61 @@ credit_to_valrdy processor_offchip_noc3_c2v( // Intantiate the actual chipset implementation `ifndef PITON_NOC_POWER_CHIPSET_TEST +`ifdef POLARA_LOOPBACK +chipset_impl_polara_loopback chipset_impl( +`else chipset_impl chipset_impl ( +`endif // ifdef POLARA_LOOPBACK `else // ifdef PITON_NOC_POWER_CHIPSET_TEST chipset_impl_noc_power_test chipset_impl ( -`endif +`endif // ifdef PITON_NOC_POWER_CHIPSET_TEST .chipset_clk (chipset_clk ), .chipset_rst_n (chipset_rst_n_ff ), +`ifndef POLARA_LOOPBACK .piton_ready_n (piton_ready_n ), - +`endif .test_start (test_start ), +`ifdef PITON_NOC_POWER_CHIPSET_TEST + .noc_power_test_hop_count (noc_power_test_hop_count), +`else +`ifndef POLARA_LOOPBACK .uart_rst_out_n (uart_rst_out_n ), .invalid_access_o (invalid_access ), -`ifdef POLARA_GATESIM + `ifdef POLARA_GATESIM .good_end(good_end), .bad_end(bad_end), .test_ena(test_ena), + `endif +`else // ifndef POLARA_LOOPBACK + .sw_channel_msb(sw[1]), + .sw_channel_lsb(sw[0]), + .sw_march(sw[2]), + .sw_go(sw[3]), +`endif // ifndef POLARA_LOOPBACK `endif -`ifdef PITON_NOC_POWER_CHIPSET_TEST - .noc_power_test_hop_count (noc_power_test_hop_count), -`endif - +`ifndef PITON_NOC_POWER_CHIPSET_TEST +`ifdef POLARA_GEN2_CHIPSET + `ifdef POLARA_GEN2_CHIPSETSE + .mig_ddr3_sys_se_clock_clk(mc_clk), + .chip_async_mux(chip_async_mux), + .chip_clk_en(chip_clk_en), + .chip_clk_mux_sel(chip_clk_mux_sel), + .chip_rst_n(chip_rst_n), + .fll_rst_n(fll_rst_n), + .fll_bypass(fll_bypass), + .fll_clkdiv(fll_clkdiv), + .fll_lock(fll_lock), + .fll_cfg_req(fll_cfg_req), + .fll_opmode(fll_opmode), + .fll_range(fll_range), + `else // POLARA_GEN2_CHIPSETSE + .mig_ddr3_sys_diff_clock_clk_n(clk_osc_n), + .mig_ddr3_sys_diff_clock_clk_p(clk_osc_p), + `endif // POLARA_GEN2_CHIPSETSE +`endif // POLARA_GEN2_CHIPSET +`endif // PITON_NOC_POWER_CHIPSET_TEST + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD @@ -1260,6 +1417,7 @@ chipset_impl_noc_power_test chipset_impl ( .intf_chipset_rdy_noc3(intf_chipset_rdy_noc3) // DRAM and I/O interfaces + `ifndef POLARA_LOOPBACK `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 , @@ -1288,11 +1446,11 @@ chipset_impl_noc_power_test chipset_impl ( .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), - `endif // XUPP3R_BOARD + `endif // XUPP3R_OR_ALVEO .ddr_odt(ddr_odt) `else // ifndef F1_BOARD .mc_clk(mc_clk), @@ -1355,17 +1513,20 @@ chipset_impl_noc_power_test chipset_impl ( `endif //ifndef F1_BOARD `endif // endif PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC - + `endif // endif POLARA_LOOPBACK + `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART , .uart_tx(uart_tx), .uart_rx(uart_rx) + `ifndef PITON_NOC_POWER_CHIPSET_TEST `ifdef PITONSYS_UART_BOOT , .uart_boot_en(uart_boot_en), .uart_timeout_en(uart_timeout_en) `endif // endif PITONSYS_UART_BOOT + `endif // PITON_NOC_POWER_CHIPSET_TEST `endif // endif PITONSYS_UART `ifdef PITONSYS_SPI @@ -1382,6 +1543,7 @@ chipset_impl_noc_power_test chipset_impl ( .sd_cmd(sd_cmd), .sd_dat(sd_dat) `endif // endif PITONSYS_SPI + `ifndef PITON_NOC_POWER_CHIPSET_TEST `ifdef PITON_FPGA_ETHERNETLITE , .net_axi_clk (net_axi_clk ), @@ -1399,8 +1561,23 @@ chipset_impl_noc_power_test chipset_impl ( .net_phy_mdio_io (net_phy_mdio_io ), .net_phy_mdc (net_phy_mdc ) - `endif // PITON_FPGA_ETHERNETLITE + `endif // PITON_FPGA_ETHERNETLITE + `endif // PITON_NOC_POWER_CHIPSET_TEST `endif // endif PITONSYS_IOCTRL + + `ifdef ALVEO_BOARD + , // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + .chip_rstn (chip_rstn) + + `endif ); @@ -1563,8 +1740,8 @@ chipset_impl_noc_power_test chipset_impl ( `ifdef GENESYS2_BOARD oled_wrapper #( - .OLED_SYS_CLK_KHZ (50000), - .OLED_SPI_CLK_KHZ (5000) + .OLED_SYS_CLK_KHZ (66667), + .OLED_SPI_CLK_KHZ (10000) ) oled_wrapper ( .sys_clk (chipset_clk ), .sys_rst_n (chipset_rst_n_ff ), diff --git a/piton/design/chipset/rtl/chipset_impl.v.pyv b/piton/design/chipset/rtl/chipset_impl.v.pyv index 1fd900c79..019a0a85b 100644 --- a/piton/design/chipset/rtl/chipset_impl.v.pyv +++ b/piton/design/chipset/rtl/chipset_impl.v.pyv @@ -62,6 +62,9 @@ // purposes // NEXYS4DDR_BOARD NEXYSVIDEO_BOARD Used to indicate which board this code is // being synthesized for. There are more than just these +// POLARA_GEN2_CHIPSET Uses specific memory controller for the chipset being implemented +// on a genesys2 board for the Polara project. +// POLARA_GEN2_CHIPSETSE Uses a single ended clock for the MIG instead of a differential clock. <% import os import sys @@ -93,6 +96,38 @@ module chipset_impl( input wire test_ena, `endif +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , + output chip_rstn , +`endif + +`ifdef POLARA_GEN2_CHIPSET +`ifdef POLARA_GEN2_CHIPSETSE + input wire mig_ddr3_sys_se_clock_clk, + output wire chip_async_mux, + output wire chip_clk_en, + output wire chip_clk_mux_sel, + output wire chip_rst_n, + output wire fll_rst_n, + output wire fll_bypass, + input wire fll_clkdiv, + input wire fll_lock, + output wire fll_cfg_req, + output wire fll_opmode, + output wire [3:0] fll_range, +`else + input wire mig_ddr3_sys_diff_clock_clk_n, + input wire mig_ddr3_sys_diff_clock_clk_p, +`endif +`endif + `ifndef PITONSYS_NO_MC `ifdef PITON_FPGA_MC_DDR3 `ifndef F1_BOARD @@ -158,11 +193,11 @@ module chipset_impl( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, -`endif // XUPP3R_BOARD +`endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -336,6 +371,14 @@ wire chip_filter_noc3_ready; wire test_good_end; wire test_bad_end; +wire int_pkt_filter_noc2_valid; +wire [`NOC_DATA_WIDTH-1:0] int_pkt_filter_noc2_data; +wire filter_int_pkt_noc2_ready; + +wire uart_merger_filter_noc2_valid; +wire [`NOC_DATA_WIDTH-1:0] uart_merger_filter_noc2_data; +wire filter_uart_merger_noc2_ready; + <% for i in range(len(devices)): if devices[i]["virtual"]: @@ -470,8 +513,13 @@ assign chip_buf_noc3_data = {`NOC_DATA_WIDTH{1'b0}}; assign uart_timeout_en = 1'b0; `else // ifdef PITONSYS_UART `ifndef PITONSYS_UART_BOOT - assign uart_boot_en = 1'b0; - assign uart_timeout_en = 1'b0; + `ifndef ALVEO_BOARD + assign uart_boot_en = 1'b0; + assign uart_timeout_en = 1'b0; + `else + assign uart_boot_en = 1'b1; + assign uart_timeout_en = 1'b0; + `endif // endif ALVEO_BOARD `endif // endif PITONSYS_UART_BOOT `endif // endif PITONSYS_UART `endif // endif PITONSYS_IOCTRL @@ -799,6 +847,105 @@ credit_to_valrdy noc3_xbar_to_%s( .m_axi_bready(m_axi_bready), .ddr_ready(ddr_ready) ); + `elsif POLARA_GEN2_CHIPSET + gen2_polara_top gen2_polara_top_i( + .ddr3_sdram_addr(ddr_addr), + .ddr3_sdram_ba(ddr_ba), + .ddr3_sdram_cas_n(ddr_cas_n), + .ddr3_sdram_ck_n(ddr_ck_n), + .ddr3_sdram_ck_p(ddr_ck_p), + .ddr3_sdram_cke(ddr_cke), + .ddr3_sdram_cs_n(ddr_cs_n), + .ddr3_sdram_dm(ddr_dm), + .ddr3_sdram_dq(ddr_dq), + .ddr3_sdram_dqs_n(ddr_dqs_n), + .ddr3_sdram_dqs_p(ddr_dqs_p), + .ddr3_sdram_odt(ddr_odt), + .ddr3_sdram_ras_n(ddr_ras_n), + .ddr3_sdram_reset_n(ddr_reset_n), + .ddr3_sdram_we_n(ddr_we_n), + + .chipset_clk(chipset_clk), + `ifdef POLARA_GEN2_CHIPSETSE + .mig_ddr3_sys_se_clock_clk(mig_ddr3_sys_se_clock_clk), + .chip_async_mux(chip_async_mux), + .chip_clk_en(chip_clk_en), + .chip_clk_mux_sel(chip_clk_mux_sel), + .chip_rst_n(chip_rst_n), + .fll_rst_n(fll_rst_n), + .fll_bypass(fll_bypass), + .fll_clkdiv(fll_clkdiv), + .fll_lock(fll_lock), + .fll_cfg_req(fll_cfg_req), + .fll_opmode(fll_opmode), + .fll_range(fll_range), + `else + .mig_ddr3_sys_diff_clock_clk_n(mig_ddr3_sys_diff_clock_clk_n), + .mig_ddr3_sys_diff_clock_clk_p(mig_ddr3_sys_diff_clock_clk_p), + `endif + .sys_rst_n(chipset_rst_n), + + .mem_flit_in_data(buf_mem_noc2_data), + .mem_flit_in_val(buf_mem_noc2_valid), + .mem_flit_in_rdy(mem_buf_noc2_ready), + + .mem_flit_out_data(mem_buf_noc3_data), + .mem_flit_out_val(mem_buf_noc3_valid), + .mem_flit_out_rdy(buf_mem_noc3_ready), + + .init_calib_complete_out(init_calib_complete), + .mem_ui_clk_sync_rst(mc_ui_clk_sync_rst), + + .uart_boot_en(uart_boot_en) + ); + `elsif ALVEO_BOARD + u280_polara_top u280_polara_i ( + + // PCIe + .pci_express_x16_rxn(pci_express_x16_rxn), + .pci_express_x16_rxp(pci_express_x16_rxp), + .pci_express_x16_txn(pci_express_x16_txn), + .pci_express_x16_txp(pci_express_x16_txp), + .pcie_perstn(pcie_perstn), + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .resetn(resetn), + + // DDR4 physicall interface + .c0_ddr4_act_n ( ddr_act_n ), // cas_n, ras_n and we_n are multiplexed in ddr4 + .c0_ddr4_adr ( ddr_addr ), + .c0_ddr4_ba ( ddr_ba ), + .c0_ddr4_bg ( ddr_bg ), // bank group address + .c0_ddr4_ck_t ( ddr_ck_p ), + .c0_ddr4_ck_c ( ddr_ck_n ), + .c0_ddr4_cke ( ddr_cke ), + .c0_ddr4_cs_n ( ddr_cs_n ), + .c0_ddr4_dq ( ddr_dq ), + .c0_ddr4_dqs_c ( ddr_dqs_n ), + .c0_ddr4_dqs_t ( ddr_dqs_p ), + .c0_ddr4_odt ( ddr_odt ), + .c0_ddr4_par ( ddr_parity ), // output wire c0_ddr4_parity + .c0_ddr4_reset_n ( ddr_reset_n ), + + // DDR4 clock & reset + .c0_sysclk_clk_p ( mc_clk_p ), + .c0_sysclk_clk_n ( mc_clk_n ), + + .c0_init_calib_complete ( init_calib_complete ), + + .chip_rstn (chip_rstn ), + .chipset_clk (chipset_clk ), + .chipset_rstn (chipset_rst_n ), + + .mem_flit_in_val(buf_mem_noc2_valid), + .mem_flit_in_data(buf_mem_noc2_data), + .mem_flit_in_rdy(mem_buf_noc2_ready), + + .mem_flit_out_val(mem_buf_noc3_valid), + .mem_flit_out_data(mem_buf_noc3_data), + .mem_flit_out_rdy(buf_mem_noc3_ready) + + ); `else mc_top mc_top( .mc_ui_clk_sync_rst(mc_ui_clk_sync_rst), @@ -996,9 +1143,9 @@ uart_top uart_top ( .xbar_uart_noc3_ready ( buf_uart_noc3_ready ), // output to noc2 - .uart_xbar_noc2_valid ( uart_filter_noc2_valid ), - .uart_xbar_noc2_data ( uart_filter_noc2_data ), - .xbar_uart_noc2_ready ( filter_uart_noc2_ready ), + .uart_xbar_noc2_valid ( uart_merger_filter_noc2_valid ), + .uart_xbar_noc2_data ( uart_merger_filter_noc2_data ), + .xbar_uart_noc2_ready ( filter_uart_merger_noc2_ready ), // input from noc3 .xbar_uart_noc3_valid ( filter_uart_noc3_valid ), @@ -1011,6 +1158,35 @@ uart_top uart_top ( assign test_start = 1'b1; `endif // endif PITONSYS_UART +int_pkt_gen int_pkt_gen ( + .fpga_clk ( chipset_clk ), + .rst_n ( chipset_rst_n ), + .noc_out_val ( int_pkt_filter_noc2_valid ), + .noc_out_data ( int_pkt_filter_noc2_data ), + .noc_out_rdy ( filter_int_pkt_noc2_ready ), + .interrupt ( uart_interrupt ), + .chip_id ( {(`NOC_CHIPID_WIDTH){1'b0}} ), + .x_pos ( `NOC_X_WIDTH'd0 ), + .y_pos ( `NOC_Y_WIDTH'd0 ), + .irq_le ( 1'b0 ), //0: level, 1: edge + .device_id ( 7'b1 ) // 32 devices +); + +noc_simple_merger uart_int_pkt_noc_simple_merger ( + .clk ( chipset_clk ), + .rst_n ( chipset_rst_n ), + .src0_merger_vr_noc_val ( int_pkt_filter_noc2_valid ), + .src0_merger_vr_noc_dat ( int_pkt_filter_noc2_data ), + .src0_merger_vr_noc_rdy ( filter_int_pkt_noc2_ready ), + .src1_merger_vr_noc_val ( uart_merger_filter_noc2_valid ), + .src1_merger_vr_noc_dat ( uart_merger_filter_noc2_data ), + .src1_merger_vr_noc_rdy ( filter_uart_merger_noc2_ready ), + .merger_dst_vr_noc_val ( uart_filter_noc2_valid ), + .merger_dst_vr_noc_dat ( uart_filter_noc2_data ), + .merger_dst_vr_noc_rdy ( filter_uart_noc2_ready ) +); + + // SPI interface `ifdef PITONSYS_SPI `ifdef PITON_FPGA_SD_BOOT @@ -1171,7 +1347,11 @@ fake_uart fake_uart ( // this is for selecting the right bootrom (1: baremetal, 0: linux) wire ariane_boot_sel; `ifdef PITON_FPGA_SYNTH - assign ariane_boot_sel = uart_boot_en; + `ifdef ALVEO_BOARD + assign ariane_boot_sel = 1'b1; + `else + assign ariane_boot_sel = uart_boot_en; + `endif `else `ifdef ARIANE_SIM_LINUX_BOOT assign ariane_boot_sel = 1'b0; diff --git a/piton/design/chipset/rtl/polara_debouncer.sv b/piton/design/chipset/rtl/polara_debouncer.sv new file mode 100644 index 000000000..152ae10e3 --- /dev/null +++ b/piton/design/chipset/rtl/polara_debouncer.sv @@ -0,0 +1,129 @@ +// Debouncer module to use for the switches in the Polara loopback chipset. +// Taken from: https://github.com/iammituraj/debouncer/blob/main/debouncer.sv +// N_BOUNCE = ceil(log_2(T_bounce / T_clk)) +// For T_bounce = 10ms and T_clk = 40MHz, this gives N_BOUNCE = 19 +/*=============================================================================================================================== + Module : Debouncer + + Description : Debouncer is used to filter bouncing found in typical switches and provide a clean, glitch-free state change. + -- Configurable bouncing interval in powers of 2 (threshold). + -- Changes state at the output based on counting the no. of times the same input is sampled consecutively. + Switch state transition appears at output only if the count crosses the threshold. + -- Debounces both assertion and release of switches. + -- Supports both pull-up and pull-down switch inputs. + -- Debouncer is designed to debounce switches with pull-down (OFF state = '0', ON state = '1'). + For pull-up switches (OFF state = '1', ON state = '0'), debounced signal should be treated as valid + only after one bouncing interval latency after reset. Because on reset, debounced signal + drives '0' by default, which is ON state for pull-up switch. This may be undesirable. + If the initial latency is undesired, IS_PULLUP parameter can be set. + + Developer : Mitu Raj, chip@chipmunklogic.com at Chipmunk Logic ™, https://chipmunklogic.com + Notes : Fully synthesisable, portable and tested code. + < 10 MHz clock is recommended for minimal resource usage assuming < 10 ms as switch bouncing time. + License : Open-source. + Date : Nov-09-2021 +===============================================================================================================================*/ + +/*------------------------------------------------------------------------------------------------------------------------------- + D E B O U N C E R +-------------------------------------------------------------------------------------------------------------------------------*/ + +module debouncer #( + + // Global Parameters + parameter N_BOUNCE = 19 , // Bouncing interval in clock cycles = 2^N_BOUNCE + parameter IS_PULLUP = 0 // Optional: '1' for pull-up switch, '0' for pull-down switch + +) + +( + input logic clk , // Clock + input logic rstn , // Active-low synchronous reset + input logic i_sig , // Bouncing signal from switch + output logic o_sig_debounced // Debounced signal +) ; + + +/*------------------------------------------------------------------------------------------------------------------------------- + Internal Registers/Signals +-------------------------------------------------------------------------------------------------------------------------------*/ +logic isig_rg, isig_sync_rg ; // Registers in 2FF Synchronizer +logic sig_rg, sig_d_rg, sig_debounced_rg ; // Registers for switch's state +logic [N_BOUNCE : 0] counter_rg ; // Counter +logic [N_BOUNCE : 0] nxt_cnt ; // Next count + + +/*------------------------------------------------------------------------------------------------------------------------------- + Synchronous logic for debouncing +-------------------------------------------------------------------------------------------------------------------------------*/ +always @(posedge clk) begin + + // Reset + if (!rstn) begin + + // Internal Registers + sig_rg <= IS_PULLUP ; + sig_d_rg <= IS_PULLUP ; + sig_debounced_rg <= IS_PULLUP ; + counter_rg <= 1 ; + + end + + // Out of reset + else begin + + // Register state of switch + sig_rg <= isig_sync_rg ; + sig_d_rg <= sig_rg ; + + // Increment counter if two consecutive states are same, otherwise reset + counter_rg <= (sig_d_rg == sig_rg) ? nxt_cnt : 1 ; + + // Counter overflow, valid state registered + if (counter_rg [N_BOUNCE]) begin + sig_debounced_rg <= sig_d_rg ; + end + + end + +end + +assign nxt_cnt = (counter_rg [N_BOUNCE])? counter_rg : (counter_rg + 1) ; + + +/*------------------------------------------------------------------------------------------------------------------------------- + 2FF Synchronizer +-------------------------------------------------------------------------------------------------------------------------------*/ +always @(posedge clk) begin + + // Reset + if (!rstn) begin + + // Internal Registers + isig_rg <= IS_PULLUP ; + isig_sync_rg <= IS_PULLUP ; + + end + + // Out of reset + else begin + + isig_rg <= i_sig ; // Metastable flop + isig_sync_rg <= isig_rg ; // Synchronizing flop + + end + +end + + +/*------------------------------------------------------------------------------------------------------------------------------- + Continuous Assignments +-------------------------------------------------------------------------------------------------------------------------------*/ +assign o_sig_debounced = sig_debounced_rg ; + + +endmodule + +/*------------------------------------------------------------------------------------------------------------------------------- + D E B O U N C E R +-------------------------------------------------------------------------------------------------------------------------------*/ diff --git a/piton/design/chipset/rtl/polara_loopback.v b/piton/design/chipset/rtl/polara_loopback.v new file mode 100644 index 000000000..c17209428 --- /dev/null +++ b/piton/design/chipset/rtl/polara_loopback.v @@ -0,0 +1,201 @@ +`include "define.tmp.h" +`include "piton_system.vh" + +// Filename: polara_loopback.v +// Author: Raphael Rowley (2024-08) +// Contact: raphael.rowley@polymtl.ca +// Description: Chipset implementation that just sends +// dummy packets into chip to test its NoC + +module chipset_impl_polara_loopback( + // Clocks and resets + input chipset_clk, + input chipset_rst_n, + + // Switches + input sw_channel_msb, + input sw_channel_lsb, + input sw_march, + input sw_go, + output sanity_is_waiting, + + // Main chip interface + /* + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3,*/ + output [64-1:0] chipset_intf_data_noc1, + output [64-1:0] chipset_intf_data_noc2, + output [64-1:0] chipset_intf_data_noc3, + output chipset_intf_val_noc1, + output chipset_intf_val_noc2, + output chipset_intf_val_noc3, + input chipset_intf_rdy_noc1, + input chipset_intf_rdy_noc2, + input chipset_intf_rdy_noc3, + + /*input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc1, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc2, + input [`NOC_DATA_WIDTH-1:0] intf_chipset_data_noc3,*/ + input [64-1:0] intf_chipset_data_noc1, + input [64-1:0] intf_chipset_data_noc2, + input [64-1:0] intf_chipset_data_noc3, + input intf_chipset_val_noc1, + input intf_chipset_val_noc2, + input intf_chipset_val_noc3, + output intf_chipset_rdy_noc1, + output intf_chipset_rdy_noc2, + output intf_chipset_rdy_noc3, + + // Chip and other BD signals + input mc_clk, // not sure if needed + input mig_ddr3_sys_se_clock_clk, + output chip_async_mux, + output chip_clk_en, + output chip_clk_mux_sel, + output chip_rst_n, + output init_calib_complete, + output test_start, + + // FLL + input fll_clkdiv, + input fll_lock, + output fll_bypass, + output fll_cfg_req, + output fll_opmode, + output [3:0] fll_range, + output fll_rst_n, + + // Just dummy signals + output uart_tx, + input uart_rx, + input uart_boot_en, + input uart_timeout_en +); + +// ///////////////////// +// Type declarations // +// ///////////////////// + +// ///////////////////////////////////////////////////////////////// +// NoC message for polara loopback +// CHIPID: 14'b10000000000000 +// XPOS: 8'd0 +// YPOS: 8'd0 +// FBITS: 4'b0010 +// PAYLOAD LENGTH: 8'd0 +// MESSAGE TYPE: MSG_TYPE_INV_FWD // Causes dummy invalidations 8'd18=8'b00010010 +// MSHR/TAG: 8'd0 +// RESERVED: 6'd0 +// ///////////////////////////////////////////////////////////////// + + wire [1:0] polara_gen2chipset_bus_i; + wire [11:0] polara_gen2chipset_bus_o; + wire chip_rst_n_inter; + + wire sw_msb_debounced; + wire sw_lsb_debounced; + wire [1:0] sw_debounced; + wire sw_march_debounced; + wire sw_go_debounced; + + reg Q1, chipset_rstn_sync; + +////////////////////// +// Sequential Logic // +////////////////////// + +///////////////////////// +// Combinational Logic // +///////////////////////// + + // Instantiate the packet generator + polara_loopback_packet_gen packet_gen_i( + .chipset_clk(chipset_clk), + .chip_rst_n(chip_rst_n_inter), + .sw_debounced(sw_debounced), + .march(sw_march_debounced), + .go(sw_go_debounced), + .sanity_is_waiting(sanity_is_waiting), + .chipset_intf_data_noc1(chipset_intf_data_noc1), + .chipset_intf_data_noc2(chipset_intf_data_noc2), + .chipset_intf_data_noc3(chipset_intf_data_noc3), + .chipset_intf_val_noc1(chipset_intf_val_noc1), + .chipset_intf_val_noc2(chipset_intf_val_noc2), + .chipset_intf_val_noc3(chipset_intf_val_noc3), + .chipset_intf_rdy_noc1(chipset_intf_rdy_noc1), + .chipset_intf_rdy_noc2(chipset_intf_rdy_noc2), + .chipset_intf_rdy_noc3(chipset_intf_rdy_noc3), + .intf_chipset_rdy_noc1(intf_chipset_rdy_noc1), + .intf_chipset_rdy_noc2(intf_chipset_rdy_noc2), + .intf_chipset_rdy_noc3(intf_chipset_rdy_noc3) + ); + + // Instantiate the block design + gen2_polara_fpga_loopback gen2_polara_fpga_i( + .bd_clk(chipset_clk), + .mig_ddr3_sys_rst_n(chipset_rstn_sync), + .polara_gen2chipset_bus_i_tri_i(polara_gen2chipset_bus_i), + .polara_gen2chipset_bus_o_tri_o(polara_gen2chipset_bus_o) + ); + + // Synchronize the reset signal and send to the rest of the blocks + always @ (posedge chipset_clk, negedge chipset_rst_n) + if(!chipset_rst_n) begin + Q1 <= 1'b0; + chipset_rstn_sync <= 1'b0; + end else begin + Q1 <= 1'b1; + chipset_rstn_sync <= Q1; + end + + // Instantiate debouncers for the 2 channel switches + debouncer debouncer_sw_msb( + .clk(chipset_clk), + .rstn(chipset_rstn_sync), + .i_sig(sw_channel_msb), + .o_sig_debounced(sw_msb_debounced)); + debouncer debouncer_sw_lsb( + .clk(chipset_clk), + .rstn(chipset_rstn_sync), + .i_sig(sw_channel_lsb), + .o_sig_debounced(sw_lsb_debounced)); + assign sw_debounced = {sw_msb_debounced, sw_lsb_debounced}; + + debouncer debouncer_sw_march( + .clk(chipset_clk), + .rstn(chipset_rstn_sync), + .i_sig(sw_march), + .o_sig_debounced(sw_march_debounced)); + debouncer debouncer_sw_go( + .clk(chipset_clk), + .rstn(chipset_rstn_sync), + .i_sig(sw_go), + .o_sig_debounced(sw_go_debounced)); + + + + // Route polara_gen2chipset_bus signals + assign chip_rst_n = chip_rst_n_inter; + assign chip_rst_n_inter = polara_gen2chipset_bus_o[0]; + assign chip_async_mux = polara_gen2chipset_bus_o[1]; + assign chip_clk_en = polara_gen2chipset_bus_o[2]; + assign chip_clk_mux_sel = polara_gen2chipset_bus_o[3]; + + assign fll_rst_n = polara_gen2chipset_bus_o[4]; + assign fll_bypass = polara_gen2chipset_bus_o[5]; + assign fll_opmode = polara_gen2chipset_bus_o[6]; + assign fll_cfg_req = polara_gen2chipset_bus_o[7]; + + assign fll_range[3:0] = polara_gen2chipset_bus_o[11:8]; + + assign polara_gen2chipset_bus_i[0] = fll_lock; + assign polara_gen2chipset_bus_i[1] = fll_clkdiv; + + + + // Assign network I/Os + assign test_start = 1'b1; + + +endmodule diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen.v b/piton/design/chipset/rtl/polara_loopback_packet_gen.v new file mode 100644 index 000000000..2cef48a2d --- /dev/null +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen.v @@ -0,0 +1,224 @@ +//`include "define.tmp.h" +//`include "piton_system.vh" + +// Filename: polara_loopback.v +// Author: Raphael Rowley (2024-09) +// Contact: raphael.rowley@polymtl.ca +// Description: Packet generation logic for polara_loopback.v +module polara_loopback_packet_gen( + input chipset_clk, + input chip_rst_n, + input [1:0] sw_debounced, + input march, + input go, + output reg sanity_is_waiting, + // Main chip interface + /* + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc1, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc2, + output reg [`NOC_DATA_WIDTH-1:0] chipset_intf_data_noc3,*/ + output reg [64-1:0] chipset_intf_data_noc1, + output reg [64-1:0] chipset_intf_data_noc2, + output reg [64-1:0] chipset_intf_data_noc3, + output reg chipset_intf_val_noc1, + output reg chipset_intf_val_noc2, + output reg chipset_intf_val_noc3, + input chipset_intf_rdy_noc1, + input chipset_intf_rdy_noc2, + input chipset_intf_rdy_noc3, + + + output intf_chipset_rdy_noc1, + output intf_chipset_rdy_noc2, + output intf_chipset_rdy_noc3 +); + // ///////////////////// + // Type declarations // + // ///////////////////// + + // ///////////////////////////////////////////////////////////////// + // NoC message for polara loopback + // CHIPID: 14'b10000000000000 + // XPOS: 8'd0 + // YPOS: 8'd0 + // FBITS: 4'b0010 + // PAYLOAD LENGTH: 8'd0 + // MESSAGE TYPE: MSG_TYPE_INV_FWD // Causes dummy invalidations 8'd18=8'b00010010 + // MSHR/TAG: 8'd0 + // RESERVED: 6'd0 + // ///////////////////////////////////////////////////////////////// + + parameter STATE_RESET = 3'b000; + parameter STATE_SEND = 3'b001; + parameter STATE_WAIT = 3'b010; + parameter STATE_SEND_HEADER = 3'b011; + parameter STATE_SEND_DATA = 3'b100; + parameter STATE_SPECIAL_WAIT = 3'b101; + + + reg [2:0] CurrentState, NextState; + //wire [`NOC_DATA_WIDTH-1:0] out_data; + reg [64-1:0] out_data, next_data; + reg [6:0] payload_count; + + reg noc_rdy; + + + + // //////////////////// + // Sequential Logic // + // //////////////////// + always @ (posedge chipset_clk, negedge chip_rst_n) + begin: SEQ + if (~chip_rst_n) + begin + CurrentState <= STATE_RESET; + out_data <= {64{1'b0}}; + payload_count <= 7'd0; + sanity_is_waiting <= 1'b1; + end + else + begin + case (CurrentState) + STATE_RESET: + begin + sanity_is_waiting <= 1'b1; + if (go) + begin + sanity_is_waiting <= 1'b0; + CurrentState <= STATE_SPECIAL_WAIT; + end + end // case: STATE_RESET + STATE_SPECIAL_WAIT: + begin + sanity_is_waiting <= 1'b0; + CurrentState <= STATE_SEND; + out_data <= {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd0, 8'd18, 8'd0, 6'd0}; + end + + STATE_WAIT: + begin + sanity_is_waiting <= 1'b0; + if (march) + begin + CurrentState <= STATE_SEND_HEADER; + out_data <= {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd65, 8'd18, 8'd0, 6'd0}; + end + else + begin + CurrentState <= STATE_SEND; + out_data <= {14'b10000000000000, 8'd0, 8'd0, 4'b0010, 8'd0, 8'd18, 8'd0, 6'd0}; + end + end + + STATE_SEND_HEADER: + begin + sanity_is_waiting <= 1'b0; + if (noc_rdy) + begin + CurrentState <= STATE_SEND_DATA; + out_data <= {64{1'b0}}; + payload_count <= 7'd0; + end + end // case: STATE_SEND_HEADER + + STATE_SEND_DATA: + begin + sanity_is_waiting <= 1'b0; + if (noc_rdy) + begin + if (payload_count == 7'd64) + begin + sanity_is_waiting <= 1'b1; + CurrentState <= STATE_RESET; + out_data <= {64{1'b0}}; + payload_count <= 7'd0; + end + else if (payload_count == 7'd0) + begin + out_data <= { {63{1'b0}} , {1'b1} }; + payload_count <= payload_count + 1'd1; + end + else + begin + out_data <= out_data << 1; + payload_count <= payload_count + 1'd1; + end + end + end // case: STATE_SEND_DATA + + STATE_SEND: + begin + sanity_is_waiting <= 1'b0; + if (noc_rdy) + begin + sanity_is_waiting <= 1'b1; + CurrentState = STATE_WAIT; + out_data <= {64{1'b0}}; + end + else + begin + CurrentState = STATE_SEND; + end + end // case: STATE_SEND + + default: // STATE_WAIT + begin + sanity_is_waiting <= 1'b1; + CurrentState <= STATE_RESET; + end + + endcase // case (CurrentState) + end // else: !if(~chip_rst_n) + end // block: SEQ + + + + + // /////////////////////// + // Combinational Logic // + // /////////////////////// + + // Demuxes to route data and valid signals + // `NOC_DATA_WIDTH = 64 + // And choose which rdy signal to monitor to transmit on + always @(*) begin : RDY_DEMUX + case(sw_debounced) + 2'h1: noc_rdy = chipset_intf_rdy_noc1; + 2'h2: noc_rdy = chipset_intf_rdy_noc2; + default: noc_rdy = chipset_intf_rdy_noc3; + endcase // case (sw_debounced) + end + + always @(*) begin : DATA_DEMUX + case(sw_debounced) + 2'h1: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = {out_data, {64{1'b0}}, {64{1'b0}} }; + 2'h2: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {64{1'b0}}, out_data, {64{1'b0}} }; + 2'h3: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {64{1'b0}}, {64{1'b0}}, out_data}; + default: {chipset_intf_data_noc1, chipset_intf_data_noc2, chipset_intf_data_noc3} = { {64{1'b0}}, {64{1'b0}}, {64{1'b0}} }; + endcase + end + + always @(*) begin : VALID_DEMUX + case(sw_debounced) + 2'h1: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = {(CurrentState != STATE_RESET), 1'b0, 1'b0 }; + 2'h2: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, (CurrentState != STATE_RESET), 1'b0 }; + 2'h3: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, (CurrentState != STATE_RESET) }; + default: {chipset_intf_val_noc1, chipset_intf_val_noc2, chipset_intf_val_noc3} = { 1'b0, 1'b0, 1'b0 }; + endcase + end + + /* + assign chipset_intf_data_noc1 = {`NOC_DATA_WIDTH{1'bx}}; + assign chipset_intf_data_noc2 = out_data; + assign chipset_intf_data_noc3 = {`NOC_DATA_WIDTH{1'bx}}; + + assign chipset_intf_val_noc1 = 1'b0; + assign chipset_intf_val_noc2 = (CurrentState != STATE_RESET); + assign chipset_intf_val_noc3 = 1'b0; + */ + assign intf_chipset_rdy_noc1 = 1'b0; + assign intf_chipset_rdy_noc2 = 1'b0; + assign intf_chipset_rdy_noc3 = 1'b0; + +endmodule // polara_loopback_packet_gen diff --git a/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v new file mode 100644 index 000000000..74d038e93 --- /dev/null +++ b/piton/design/chipset/rtl/polara_loopback_packet_gen_tb.v @@ -0,0 +1,121 @@ +`timescale 1ns / 1ps + +// Filename: polara_loopback_packet_gen_tb.v +// Author: Raphael Rowley (2024-09) +// Contact: raphael.rowley@polymtl.ca +// Description: Testbench to functionnally simulate the packet gen logic for polara_loopback.v + +module polara_loopback_packet_gen_tb(); + + // ///////////////////// + // Type declarations // + // ///////////////////// + reg chipset_clk; + reg chip_rst_n_inter; + reg [1:0] sw_debounced; + reg march; + reg go; + + wire sanity; + + wire [64-1:0] chipset_intf_data_noc1; + wire [64-1:0] chipset_intf_data_noc2; + wire [64-1:0] chipset_intf_data_noc3; + + wire chipset_intf_val_noc1; + wire chipset_intf_val_noc2; + wire chipset_intf_val_noc3; + + reg chipset_intf_rdy_noc1; + reg chipset_intf_rdy_noc2; + reg chipset_intf_rdy_noc3; + + wire intf_chipset_rdy_noc1; + wire intf_chipset_rdy_noc2; + wire intf_chipset_rdy_noc3; + + // Instantiate DUT + polara_loopback_packet_gen dut( + .chipset_clk(chipset_clk), + .chip_rst_n(chip_rst_n_inter), + .sw_debounced(sw_debounced), + .march(march), + .go(go), + .sanity_is_waiting(sanity), + .chipset_intf_data_noc1(chipset_intf_data_noc1), + .chipset_intf_data_noc2(chipset_intf_data_noc2), + .chipset_intf_data_noc3(chipset_intf_data_noc3), + .chipset_intf_val_noc1(chipset_intf_val_noc1), + .chipset_intf_val_noc2(chipset_intf_val_noc2), + .chipset_intf_val_noc3(chipset_intf_val_noc3), + .chipset_intf_rdy_noc1(chipset_intf_rdy_noc1), + .chipset_intf_rdy_noc2(chipset_intf_rdy_noc2), + .chipset_intf_rdy_noc3(chipset_intf_rdy_noc3), + .intf_chipset_rdy_noc1(intf_chipset_rdy_noc1), + .intf_chipset_rdy_noc2(intf_chipset_rdy_noc2), + .intf_chipset_rdy_noc3(intf_chipset_rdy_noc3) + ); + // Clock gen + initial begin + assign chipset_clk = 1'b0; + forever #12.5 assign chipset_clk = ~chipset_clk; + end + + // Reset generation + initial begin + chip_rst_n_inter = 1'b0; + #50 + chip_rst_n_inter = 1'b1; + $display("rst_n is over: %h", chip_rst_n_inter); + #50 + $display("Current state should be 1, it is: %h", dut.CurrentState); + + end + + // Stimulus + initial begin + sw_debounced = 2'b01; + chipset_intf_rdy_noc1 = 1'b0; + chipset_intf_rdy_noc2 = 1'b0; + chipset_intf_rdy_noc3 = 1'b0; + march = 1'b0; + go = 1'b1; + + #150 + chipset_intf_rdy_noc1 = 1'b1; + #150 + go = 1'b0; + chip_rst_n_inter = 1'b0; + chipset_intf_rdy_noc1 = 1'b0; + march = 1'b1; + #50 + go = 1'b1; + #50 + chip_rst_n_inter = 1'b1; + #50 + chipset_intf_rdy_noc1 = 1'b1; + #500 + chipset_intf_rdy_noc1 = 1'b0; + #500 + chipset_intf_rdy_noc1 = 1'b1; + #2000 + chip_rst_n_inter = 1'b0; + go = 1'b0; + #100 + chip_rst_n_inter = 1'b1; + $display("rst_n is over: %h", chip_rst_n_inter); + #50 + $display("Current state should be 1, it is: %h", dut.CurrentState); + #400 + go = 1'b1; + #400 + go = 1'b0; + #2000 + go = 1'b1; + #1000 + $finish; + + end + + +endmodule // polara_loopback_packet_gen_tb diff --git a/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv b/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv index 88b0b97d5..4c8d3bb40 100644 --- a/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv +++ b/piton/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv @@ -129,6 +129,7 @@ always_comb begin ie_new = '0; ie_we = '0; ie_re_o = '0; + ip_re_o = '0; threshold_new = '0; threshold_we = '0; threshold_re_o = '0; diff --git a/piton/design/chipset/xilinx/alveou280/.gitignore b/piton/design/chipset/xilinx/alveou280/.gitignore new file mode 100644 index 000000000..9f9934c3f --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/.gitignore @@ -0,0 +1,2 @@ +!ip_cores +polara_fpga \ No newline at end of file diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci new file mode 100644 index 000000000..2b46f7650 --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + afifo_w64_d128_std + + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 7 + BlankString + 64 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 64 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtexuplusHBM + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x72 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1 + 7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 7 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 7 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + afifo_w64_d128_std + 64 + false + 7 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 125 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 124 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 64 + 128 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 64 + 128 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 7 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 7 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtexuplusHBM + xilinx.com:au280:part0:1.2 + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci new file mode 100644 index 000000000..e25583f1d --- /dev/null +++ b/piton/design/chipset/xilinx/alveou280/ip_cores/clk_mmcm/clk_mmcm.xci @@ -0,0 +1,823 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_mmcm + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 100.000 + 0000 + 0000 + 50.00000 + 0000 + 0000 + 250.00000 + BUFG + 50.0 + false + 50.00000 + 0.000 + 50.000 + 50 + 0.000 + 1 + 0000 + 0000 + 50.00000 + BUFG + 50.0 + false + 250.00000 + 0.000 + 50.000 + 250.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 50.00000 + 0.000 + 50.000 + 50 + 0.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + 0000 + 0000 + 25.00000 + BUFG + 50.0 + false + 100.00000 + 180.000 + 50.000 + 100.000 + 180.000 + 1 + 1 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 25.00000 + 0.000 + 50.000 + 25.000 + 0.000 + 1 + 1 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + VCO + clk_in_sel + chipset_clk + mc_sys_clk + sd_sys_clk + chipset_passthru_clk + chipset_passthru_clk_n + net_phy_clk + net_axi_clk + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.2 + 1.0 + 0.5 + 0.5 + 2.0 + 0.5 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_____________100_______________35 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 10.000 + 0.000 + FALSE + 10.000 + 10.000 + 20.000 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 20 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + 10 + 0.500 + 180.000 + FALSE + 40 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.004 + 0.010 + FALSE + 128.000 + 2.000 + 7 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + chipset_clk__50.00000______0.000______50.0______147.729_____98.575 + mc_sys_clk__250.00000______0.000______50.0______108.624_____98.575 + sd_sys_clk__50.00000______0.000______50.0______147.729_____98.575 + chipset_passthru_clk__100.00000______0.000______50.0______129.254_____98.575 + chipset_passthru_clk_n__100.00000____180.000______50.0______129.254_____98.575 + net_phy_clk__25.00000______0.000______50.0______168.830_____98.575 + net_axi_clk__100.00000______0.000______50.0______129.254_____98.575 + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1600.000 + 800.000 + clk_mmcm + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 35 + 35 + 100.000 + 100.000 + BUFG + 147.729 + false + 98.575 + 50.000 + 50 + 0.000 + 1 + true + BUFG + 108.624 + false + 98.575 + 50.000 + 250.000 + 0.000 + 1 + true + BUFG + 147.729 + false + 98.575 + 50.000 + 50 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 180.000 + 1 + true + BUFG + 168.830 + false + 98.575 + 50.000 + 25.000 + 0.000 + 1 + true + BUFG + 129.254 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + 600.000 + Custom + Custom + clk_in_sel + chipset_clk + false + mc_sys_clk + false + sd_sys_clk + false + chipset_passthru_clk + false + chipset_passthru_clk_n + false + net_phy_clk + false + net_axi_clk + false + CLK_VALID + auto + clk_mmcm + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + PS + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + false + 10.000 + 10.000 + 20.000 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 20 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + 10 + 0.500 + 180.000 + false + 40 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.004 + 0.010 + false + 7 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + virtexuplusHBM + + + xcu280 + fsvh2892 + VERILOG + + MIXED + -2L + + E + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/chipset/xilinx/genesys2/constraints.xdc b/piton/design/chipset/xilinx/genesys2/constraints.xdc index 79d4a823a..ef12cabc6 100644 --- a/piton/design/chipset/xilinx/genesys2/constraints.xdc +++ b/piton/design/chipset/xilinx/genesys2/constraints.xdc @@ -23,28 +23,53 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# Debug +set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS18} [get_ports dbg0] +set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports dbg1] +set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports dbg2] +set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18} [get_ports dbg3] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports dbg4] +set_property -dict {PACKAGE_PIN M23 IOSTANDARD LVCMOS18} [get_ports dbg5] +set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS18} [get_ports dbg6] +set_property -dict {PACKAGE_PIN J28 IOSTANDARD LVCMOS18} [get_ports dbg7] +set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports dbg8] +set_property -dict {PACKAGE_PIN L27 IOSTANDARD LVCMOS18} [get_ports dbg9] +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS18} [get_ports dbg10] +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18} [get_ports dbg11] +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports dbg12] +set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS18} [get_ports dbg13] +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS18} [get_ports dbg14] +set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS18} [get_ports dbg15] + # Clock signals set_property IOSTANDARD LVDS [get_ports clk_osc_p] set_property PACKAGE_PIN AD12 [get_ports clk_osc_p] set_property PACKAGE_PIN AD11 [get_ports clk_osc_n] set_property IOSTANDARD LVDS [get_ports clk_osc_n] - +# Line needed to avoid placer failure set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mmcm/inst/clk_in1_clk_mmcm] # Non-MMCM clock constraints -create_clock -period 5.000 -name passthru_chipset_clk_p -waveform {0.000 2.500} [get_ports passthru_chipset_clk_p] -create_clock -period 5.000 -name passthru_chipset_clk_n -waveform {2.500 5.000} [get_ports passthru_chipset_clk_n] -create_clock -period 5.000 -name passthru_chipset_clk -waveform {0.000 2.500} [get_pins passthru_chipset_clk_ibufgds/O] -create_clock -period 5.000 -name chipset_passthru_clk_p -waveform {0.000 2.500} [get_ports chipset_passthru_clk_p] -create_clock -period 5.000 -name chipset_passthru_clk_n -waveform {2.500 5.000} [get_ports chipset_passthru_clk_n] +#create_clock -period 5.000 -name passthru_chipset_clk_p -waveform {0.000 2.500} [get_ports passthru_chipset_clk_p] +#create_clock -period 5.000 -name passthru_chipset_clk_n -waveform {2.500 5.000} [get_ports passthru_chipset_clk_n] +#create_clock -period 5.000 -name passthru_chipset_clk -waveform {0.000 2.500} [get_pins passthru_chipset_clk_ibufgds/O] +#create_clock -period 5.000 -name chipset_passthru_clk_p -waveform {0.000 2.500} [get_ports chipset_passthru_clk_p] +#create_clock -period 5.000 -name chipset_passthru_clk_n -waveform {2.500 5.000} [get_ports chipset_passthru_clk_n] +# Assuming that io_clk has to be created like chipset_passthru_clk_p (RR 2024/05/21) +# 66.666 MHz +#create_clock -period 15.000 -name io_clk -waveform {0.000 7.500} [get_ports io_clk] +#create_clock -period 15.000 -name core_ref_clk -waveform {0.000 7.500} [get_ports core_ref_clk] +create_clock -period 125.000 -name io_clk -waveform {0.000 62.500} [get_ports io_clk] +create_clock -period 25.000 -name core_ref_clk -waveform {0.000 12.500} [get_ports core_ref_clk] + # Constraint RGMII interface -create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] -set_output_delay -clock txc_gen 2.000 [get_ports net_phy_txctl] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[0]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[1]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[2]}] -set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[3]}] +#create_generated_clock -name txc_gen -source [get_pins net_phy_txc_oddr/C] -multiply_by 1 [get_ports net_phy_txc] +#set_output_delay -clock txc_gen 2.000 [get_ports net_phy_txctl] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[0]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[1]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[2]}] +#set_output_delay -clock txc_gen 2.000 [get_ports {net_phy_txd[3]}] # Reset set_property IOSTANDARD LVCMOS33 [get_ports rst_n] @@ -55,8 +80,8 @@ set_false_path -to [get_cells -hierarchical *afifo_ui_rst_r*] set_false_path -to [get_cells -hierarchical *ui_clk_sync_rst_r*] set_false_path -to [get_cells -hierarchical *ui_clk_syn_rst_delayed*] set_false_path -to [get_cells -hierarchical *init_calib_complete_f*] -set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] -set_false_path -from [get_clocks net_axi_clk_clk_mmcm] -to [get_clocks chipset_clk_clk_mmcm] +#set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks net_axi_clk_clk_mmcm] +#set_false_path -from [get_clocks net_axi_clk_clk_mmcm] -to [get_clocks chipset_clk_clk_mmcm] @@ -68,21 +93,22 @@ set_property IOSTANDARD LVCMOS33 [get_ports uart_tx] set_property PACKAGE_PIN Y23 [get_ports uart_tx] # Switches +# sw[7] and sw[6] powered by 3.3V, the rest by VADJ set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] set_property PACKAGE_PIN P27 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] set_property PACKAGE_PIN P26 [get_ports {sw[6]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[5]}] set_property PACKAGE_PIN P19 [get_ports {sw[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[4]}] set_property PACKAGE_PIN N19 [get_ports {sw[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[3]}] set_property PACKAGE_PIN K19 [get_ports {sw[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[2]}] set_property PACKAGE_PIN H24 [get_ports {sw[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[1]}] set_property PACKAGE_PIN G25 [get_ports {sw[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {sw[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {sw[0]}] set_property PACKAGE_PIN G19 [get_ports {sw[0]}] # Loopback control for UART @@ -94,22 +120,22 @@ set_property PACKAGE_PIN G19 [get_ports {sw[0]}] #set_property PACKAGE_PIN E18 [get_ports pin_soft_rst] # SD -set_property IOSTANDARD LVCMOS33 [get_ports sd_clk_out] -set_property PACKAGE_PIN R28 [get_ports sd_clk_out] -set_property IOSTANDARD LVCMOS33 [get_ports sd_cmd] -set_property PACKAGE_PIN R29 [get_ports sd_cmd] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[0]}] -set_property PACKAGE_PIN R26 [get_ports {sd_dat[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[1]}] -set_property PACKAGE_PIN R30 [get_ports {sd_dat[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[2]}] -set_property PACKAGE_PIN P29 [get_ports {sd_dat[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[3]}] -set_property PACKAGE_PIN T30 [get_ports {sd_dat[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports sd_reset] -set_property PACKAGE_PIN AE24 [get_ports sd_reset] -set_property IOSTANDARD LVCMOS33 [get_ports sd_cd] -set_property PACKAGE_PIN P28 [get_ports sd_cd] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_clk_out] +#set_property PACKAGE_PIN R28 [get_ports sd_clk_out] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_cmd] +#set_property PACKAGE_PIN R29 [get_ports sd_cmd] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[0]}] +#set_property PACKAGE_PIN R26 [get_ports {sd_dat[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[1]}] +#set_property PACKAGE_PIN R30 [get_ports {sd_dat[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[2]}] +#set_property PACKAGE_PIN P29 [get_ports {sd_dat[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sd_dat[3]}] +#set_property PACKAGE_PIN T30 [get_ports {sd_dat[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_reset] +#set_property PACKAGE_PIN AE24 [get_ports sd_reset] +#set_property IOSTANDARD LVCMOS33 [get_ports sd_cd] +#set_property PACKAGE_PIN P28 [get_ports sd_cd] ## LEDs @@ -141,377 +167,638 @@ set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS18} [get_ports oled_vdd_n] ## Buttons +# powered by VADJ set_property PACKAGE_PIN M20 [get_ports btnl] -set_property IOSTANDARD LVCMOS25 [get_ports btnl] +set_property IOSTANDARD LVCMOS18 [get_ports btnl] set_property PACKAGE_PIN C19 [get_ports btnr] -set_property IOSTANDARD LVCMOS25 [get_ports btnr] +set_property IOSTANDARD LVCMOS18 [get_ports btnr] set_property PACKAGE_PIN M19 [get_ports btnd] -set_property IOSTANDARD LVCMOS25 [get_ports btnd] +set_property IOSTANDARD LVCMOS18 [get_ports btnd] set_property PACKAGE_PIN B19 [get_ports btnu] -set_property IOSTANDARD LVCMOS25 [get_ports btnu] +set_property IOSTANDARD LVCMOS18 [get_ports btnu] +# btnc +# piton_prsnt_n for Genesys2 chipset target (RR 2024/05/28) +#set_property PACKAGE_PIN E18 [get_ports piton_prsnt_n] +#set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] ## Ethernet # NOTUSED? set_property PACKAGE_PIN AK16 [get_ports net_ip2intc_irpt] # NOTUSED? set_property IOSTANDARD LVCMOS18 [get_ports net_ip2intc_irpt] # NOTUSED? set_property PULLUP true [get_ports net_ip2intc_irpt] -set_property PACKAGE_PIN AF12 [get_ports net_phy_mdc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdc] -set_property PACKAGE_PIN AG12 [get_ports net_phy_mdio_io] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdio_io] -set_property PACKAGE_PIN AH24 [get_ports net_phy_rst_n] -set_property IOSTANDARD LVCMOS33 [get_ports net_phy_rst_n] +#set_property PACKAGE_PIN AF12 [get_ports net_phy_mdc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdc] +#set_property PACKAGE_PIN AG12 [get_ports net_phy_mdio_io] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_mdio_io] +#set_property PACKAGE_PIN AH24 [get_ports net_phy_rst_n] +#set_property IOSTANDARD LVCMOS33 [get_ports net_phy_rst_n] #set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { ETH_PMEB }]; #IO_L1N_T0_32 Sch=eth_pmeb -set_property PACKAGE_PIN AG10 [get_ports net_phy_rxc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxc] -set_property PACKAGE_PIN AH11 [get_ports net_phy_rxctl] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxctl] -set_property PACKAGE_PIN AJ14 [get_ports {net_phy_rxd[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[0]}] -set_property PACKAGE_PIN AH14 [get_ports {net_phy_rxd[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[1]}] -set_property PACKAGE_PIN AK13 [get_ports {net_phy_rxd[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[2]}] -set_property PACKAGE_PIN AJ13 [get_ports {net_phy_rxd[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[3]}] -set_property PACKAGE_PIN AE10 [get_ports net_phy_txc] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txc] -set_property PACKAGE_PIN AJ12 [get_ports {net_phy_txd[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[0]}] -set_property PACKAGE_PIN AK11 [get_ports {net_phy_txd[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[1]}] -set_property PACKAGE_PIN AJ11 [get_ports {net_phy_txd[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[2]}] -set_property PACKAGE_PIN AK10 [get_ports {net_phy_txd[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[3]}] -set_property PACKAGE_PIN AK14 [get_ports net_phy_txctl] -set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] +#set_property PACKAGE_PIN AG10 [get_ports net_phy_rxc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxc] +#set_property PACKAGE_PIN AH11 [get_ports net_phy_rxctl] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_rxctl] +#set_property PACKAGE_PIN AJ14 [get_ports {net_phy_rxd[0]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[0]}] +#set_property PACKAGE_PIN AH14 [get_ports {net_phy_rxd[1]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[1]}] +#set_property PACKAGE_PIN AK13 [get_ports {net_phy_rxd[2]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[2]}] +#set_property PACKAGE_PIN AJ13 [get_ports {net_phy_rxd[3]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_rxd[3]}] +#set_property PACKAGE_PIN AE10 [get_ports net_phy_txc] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txc] +#set_property PACKAGE_PIN AJ12 [get_ports {net_phy_txd[0]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[0]}] +#set_property PACKAGE_PIN AK11 [get_ports {net_phy_txd[1]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[1]}] +#set_property PACKAGE_PIN AJ11 [get_ports {net_phy_txd[2]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[2]}] +#set_property PACKAGE_PIN AK10 [get_ports {net_phy_txd[3]}] +#set_property IOSTANDARD LVCMOS15 [get_ports {net_phy_txd[3]}] +#set_property PACKAGE_PIN AK14 [get_ports net_phy_txctl] +#set_property IOSTANDARD LVCMOS15 [get_ports net_phy_txctl] # FMC Clocks -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_n] -set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_p] -set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_n] -set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_p] +#set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_n] +#set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports chipset_passthru_clk_p] +#set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_n] +#set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVDS_25} [get_ports passthru_chipset_clk_p] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports core_ref_clk] +set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS18} [get_ports io_clk] # FMC Signals -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] -set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] -set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] -set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] -set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] -set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] -set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] -set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] -set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] -set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[2]}] -set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] -set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] -set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] -set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[0]}] -set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] -set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] -set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] -set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] -set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] -set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] -set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] -set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] -set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] -set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] -set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] -set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] -set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] -set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] -set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] -set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] -set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] -set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] -set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] -set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] -set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] -set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] -set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] -set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] -set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] -set_property PACKAGE_PIN H22 [get_ports {passthru_chipset_data_n[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[6]}] -set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] -set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] -set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] -set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] -set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] -set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] -set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] -set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] -set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] -set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] -set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] -set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] -set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] -set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] -set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] -set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] -set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] -set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] -set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] -set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] -set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] -set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] -set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] -set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] -set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] -set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] -set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] -set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] -set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] -set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] -set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] -set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] -set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] -set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] -set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] -set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] -set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] -set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] -set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] -set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] -set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] -set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] -set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] -set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] -set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] -set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] -set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] -set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] -set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] -set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] -set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] -set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] -set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] -set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] -set_property IOSTANDARD LVCMOS25 [get_ports piton_prsnt_n] -set_property PULLUP true [get_ports piton_prsnt_n] -set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS25 } [get_ports { F47_P }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[29]}] -set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] -set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] -set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] -set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] -set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] -set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] -set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] -set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] -set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] -set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] -set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] -set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] -set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] -set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] -set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] -set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] -set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] -set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] -set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] -set_property PACKAGE_PIN F13 [get_ports piton_ready_n] -set_property IOSTANDARD LVCMOS25 [get_ports piton_ready_n] -set_property PULLUP true [get_ports piton_ready_n] -set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS25} [get_ports chipset_prsnt_n] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[7]}] -set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] -set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] -set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] -set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] -set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] -set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] -set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] -set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] -set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] -set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] -set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] -set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] -set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] -set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] -set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] -set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] -set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] -set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] -set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] -set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] -set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] -set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] -set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] -set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] -set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] -set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] -set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] -set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] -set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] -set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] -set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] -set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] -set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] -set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] -set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] -set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] -set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] -set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] -set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] -set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS25 } [get_ports { F79_N }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] -set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS25 } [get_ports { F79_P }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18} [get_ports chip_async_mux] +set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports chip_clk_en] +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS18} [get_ports chip_clk_mux_sel] +set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS18} [get_ports chip_rst_n] +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS18} [get_ports fll_rst_n] +set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS18} [get_ports fll_bypass] +set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports fll_clkdiv] +set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports fll_lock] +set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports fll_cfg_req] +set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS18} [get_ports fll_opmode] +set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS18} [get_ports {fll_range[3]}] +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports {fll_range[2]}] +set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS18} [get_ports {fll_range[1]}] +set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS18} [get_ports {fll_range[0]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[11]}] +#set_property PACKAGE_PIN D27 [get_ports {chipset_passthru_data_p[11]}] +#set_property PACKAGE_PIN C27 [get_ports {chipset_passthru_data_n[11]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[11]}] +set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[11]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[0]}] +#set_property PACKAGE_PIN D26 [get_ports {passthru_chipset_credit_back_p[0]}] +#set_property PACKAGE_PIN C26 [get_ports {passthru_chipset_credit_back_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[0]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[0]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[16]}] +#set_property PACKAGE_PIN H30 [get_ports {chipset_passthru_data_p[16]}] +#set_property PACKAGE_PIN G30 [get_ports {chipset_passthru_data_n[16]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[16]}] +set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[16]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[12]}] +#set_property PACKAGE_PIN E29 [get_ports {chipset_passthru_data_p[12]}] +#set_property PACKAGE_PIN E30 [get_ports {chipset_passthru_data_n[12]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[12]}] +set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[12]}] + +#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS25 } [get_ports { F4_N }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] +#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS25 } [get_ports { F4_P }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[2]}] +#set_property PACKAGE_PIN B30 [get_ports {passthru_chipset_credit_back_p[2]}] +#set_property PACKAGE_PIN A30 [get_ports {passthru_chipset_credit_back_n[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[2]}] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[2]}] +#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS25 } [get_ports { F6_N }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] +#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS25 } [get_ports { F6_P }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[0]}] +#set_property PACKAGE_PIN F25 [get_ports {chipset_passthru_channel_p[0]}] +#set_property PACKAGE_PIN E25 [get_ports {chipset_passthru_channel_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[0]}] +set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_channel[0]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[29]}] +#set_property PACKAGE_PIN C29 [get_ports {passthru_chipset_data_p[29]}] +#set_property PACKAGE_PIN B29 [get_ports {passthru_chipset_data_n[29]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[29]}] +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[29]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[0]}] +#set_property PACKAGE_PIN B28 [get_ports {chipset_passthru_data_p[0]}] +#set_property PACKAGE_PIN A28 [get_ports {chipset_passthru_data_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[0]}] +set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[0]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[30]}] +#set_property PACKAGE_PIN B27 [get_ports {passthru_chipset_data_p[30]}] +#set_property PACKAGE_PIN A27 [get_ports {passthru_chipset_data_n[30]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[30]}] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[30]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[31]}] +#set_property PACKAGE_PIN A25 [get_ports {chipset_passthru_data_p[31]}] +#set_property PACKAGE_PIN A26 [get_ports {chipset_passthru_data_n[31]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[31]}] +set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[31]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[9]}] +#set_property PACKAGE_PIN F26 [get_ports {chipset_passthru_data_p[9]}] +#set_property PACKAGE_PIN E26 [get_ports {chipset_passthru_data_n[9]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[9]}] +set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[9]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[20]}] +#set_property PACKAGE_PIN E24 [get_ports {passthru_chipset_data_p[20]}] +#set_property PACKAGE_PIN D24 [get_ports {passthru_chipset_data_n[20]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[20]}] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[20]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[25]}] +#set_property PACKAGE_PIN C24 [get_ports {passthru_chipset_data_p[25]}] +#set_property PACKAGE_PIN B24 [get_ports {passthru_chipset_data_n[25]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[25]}] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[25]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[25]}] +#set_property PACKAGE_PIN B23 [get_ports {chipset_passthru_data_p[25]}] +#set_property PACKAGE_PIN A23 [get_ports {chipset_passthru_data_n[25]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[25]}] +set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[25]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[15]}] +#set_property PACKAGE_PIN E23 [get_ports {passthru_chipset_data_p[15]}] +#set_property PACKAGE_PIN D23 [get_ports {passthru_chipset_data_n[15]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[15]}] +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[15]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[16]}] +#set_property PACKAGE_PIN F21 [get_ports {passthru_chipset_data_p[16]}] +#set_property PACKAGE_PIN E21 [get_ports {passthru_chipset_data_n[16]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[16]}] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[16]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[21]}] +#set_property PACKAGE_PIN D17 [get_ports {passthru_chipset_data_p[21]}] +#set_property PACKAGE_PIN D18 [get_ports {passthru_chipset_data_n[21]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[21]}] +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[21]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[14]}] +#set_property PACKAGE_PIN H21 [get_ports {passthru_chipset_data_p[14]}] +#set_property PACKAGE_PIN H22 [get_ports {passthru_chipset_data_n[14]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[14]}] +set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[14]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[6]}] +#set_property PACKAGE_PIN G22 [get_ports {chipset_passthru_data_p[6]}] +#set_property PACKAGE_PIN F22 [get_ports {chipset_passthru_data_n[6]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[6]}] +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[6]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[11]}] +#set_property PACKAGE_PIN L17 [get_ports {passthru_chipset_data_p[11]}] +#set_property PACKAGE_PIN L18 [get_ports {passthru_chipset_data_n[11]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[11]}] +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[11]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[7]}] +#set_property PACKAGE_PIN J17 [get_ports {passthru_chipset_data_p[7]}] +#set_property PACKAGE_PIN H17 [get_ports {passthru_chipset_data_n[7]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[7]}] +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[7]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[13]}] +#set_property PACKAGE_PIN G17 [get_ports {passthru_chipset_data_p[13]}] +#set_property PACKAGE_PIN F17 [get_ports {passthru_chipset_data_n[13]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[13]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[13]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[8]}] +#set_property PACKAGE_PIN H20 [get_ports {passthru_chipset_data_p[8]}] +#set_property PACKAGE_PIN G20 [get_ports {passthru_chipset_data_n[8]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[8]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[8]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[9]}] +#set_property PACKAGE_PIN D22 [get_ports {passthru_chipset_data_p[9]}] +#set_property PACKAGE_PIN C22 [get_ports {passthru_chipset_data_n[9]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[9]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[9]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[18]}] +#set_property PACKAGE_PIN B22 [get_ports {passthru_chipset_data_p[18]}] +#set_property PACKAGE_PIN A22 [get_ports {passthru_chipset_data_n[18]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[18]}] +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[18]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[22]}] +#set_property PACKAGE_PIN A20 [get_ports {passthru_chipset_data_p[22]}] +#set_property PACKAGE_PIN A21 [get_ports {passthru_chipset_data_n[22]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[22]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[22]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[31]}] +#set_property PACKAGE_PIN J19 [get_ports {passthru_chipset_data_p[31]}] +#set_property PACKAGE_PIN H19 [get_ports {passthru_chipset_data_n[31]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[31]}] +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[31]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[2]}] +#set_property PACKAGE_PIN B18 [get_ports {chipset_passthru_data_p[2]}] +#set_property PACKAGE_PIN A18 [get_ports {chipset_passthru_data_n[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[2]}] +set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[2]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[0]}] +#set_property PACKAGE_PIN A16 [get_ports {passthru_chipset_data_p[0]}] +#set_property PACKAGE_PIN A17 [get_ports {passthru_chipset_data_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[0]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[0]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[6]}] +#set_property PACKAGE_PIN C17 [get_ports {passthru_chipset_data_p[6]}] +#set_property PACKAGE_PIN B17 [get_ports {passthru_chipset_data_n[6]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[6]}] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[6]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[10]}] +#set_property PACKAGE_PIN K18 [get_ports {passthru_chipset_data_p[10]}] +#set_property PACKAGE_PIN J18 [get_ports {passthru_chipset_data_n[10]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[10]}] +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[10]}] + + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[1]}] +#set_property PACKAGE_PIN D16 [get_ports {chipset_passthru_credit_back_p[1]}] +#set_property PACKAGE_PIN C16 [get_ports {chipset_passthru_credit_back_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[1]}] +set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[1]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[15]}] +#set_property PACKAGE_PIN K28 [get_ports {chipset_passthru_data_p[15]}] +#set_property PACKAGE_PIN K29 [get_ports {chipset_passthru_data_n[15]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[15]}] +set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[15]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[13]}] +#set_property PACKAGE_PIN M28 [get_ports {chipset_passthru_data_p[13]}] +#set_property PACKAGE_PIN L28 [get_ports {chipset_passthru_data_n[13]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[13]}] +set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[13]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[24]}] +#set_property PACKAGE_PIN P21 [get_ports {chipset_passthru_data_p[24]}] +#set_property PACKAGE_PIN P22 [get_ports {chipset_passthru_data_n[24]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[24]}] +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[24]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[26]}] +#set_property PACKAGE_PIN N25 [get_ports {chipset_passthru_data_p[26]}] +#set_property PACKAGE_PIN N26 [get_ports {chipset_passthru_data_n[26]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[26]}] +set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[26]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[18]}] +#set_property PACKAGE_PIN M24 [get_ports {chipset_passthru_data_p[18]}] +#set_property PACKAGE_PIN M25 [get_ports {chipset_passthru_data_n[18]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[18]}] +set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[18]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[17]}] +#set_property PACKAGE_PIN J29 [get_ports {chipset_passthru_data_p[17]}] +#set_property PACKAGE_PIN H29 [get_ports {chipset_passthru_data_n[17]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[17]}] +set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[17]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[19]}] +#set_property PACKAGE_PIN N29 [get_ports {chipset_passthru_data_p[19]}] +#set_property PACKAGE_PIN N30 [get_ports {chipset_passthru_data_n[19]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[19]}] +set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[19]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[1]}] +#set_property PACKAGE_PIN M29 [get_ports {chipset_passthru_data_p[1]}] +#set_property PACKAGE_PIN M30 [get_ports {chipset_passthru_data_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[1]}] +set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[1]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[10]}] +#set_property PACKAGE_PIN J27 [get_ports {chipset_passthru_data_p[10]}] +#set_property PACKAGE_PIN J28 [get_ports {chipset_passthru_data_n[10]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[10]}] +set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[10]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[14]}] +#set_property PACKAGE_PIN L30 [get_ports {chipset_passthru_data_p[14]}] +#set_property PACKAGE_PIN K30 [get_ports {chipset_passthru_data_n[14]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[14]}] +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[14]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[28]}] +#set_property PACKAGE_PIN N21 [get_ports {chipset_passthru_data_p[28]}] +#set_property PACKAGE_PIN N22 [get_ports {chipset_passthru_data_n[28]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[28]}] +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[28]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[30]}] +#set_property PACKAGE_PIN P23 [get_ports {chipset_passthru_data_p[30]}] +#set_property PACKAGE_PIN N24 [get_ports {chipset_passthru_data_n[30]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[30]}] +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[30]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[22]}] +#set_property PACKAGE_PIN L26 [get_ports {chipset_passthru_data_p[22]}] +#set_property PACKAGE_PIN L27 [get_ports {chipset_passthru_data_n[22]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[22]}] +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[22]}] + +#set_property PACKAGE_PIN J26 [get_ports piton_prsnt_n] +#set_property IOSTANDARD LVCMOS18 [get_ports piton_prsnt_n] +#set_property PULLUP true [get_ports piton_prsnt_n] +#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS25 } [get_ports { F47_P }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[29]}] +#set_property PACKAGE_PIN N27 [get_ports {chipset_passthru_data_p[29]}] +#set_property PACKAGE_PIN M27 [get_ports {chipset_passthru_data_n[29]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[29]}] +set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[29]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_n[1]}] +#set_property PACKAGE_PIN J21 [get_ports {passthru_chipset_credit_back_p[1]}] +#set_property PACKAGE_PIN J22 [get_ports {passthru_chipset_credit_back_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_credit_back_p[1]}] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_credit_back[1]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_n[1]}] +#set_property PACKAGE_PIN M22 [get_ports {chipset_passthru_channel_p[1]}] +#set_property PACKAGE_PIN M23 [get_ports {chipset_passthru_channel_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_channel_p[1]}] +set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_channel[1]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[20]}] +#set_property PACKAGE_PIN C25 [get_ports {chipset_passthru_data_p[20]}] +#set_property PACKAGE_PIN B25 [get_ports {chipset_passthru_data_n[20]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[20]}] +set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[20]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[28]}] +#set_property PACKAGE_PIN E19 [get_ports {passthru_chipset_data_p[28]}] +#set_property PACKAGE_PIN D19 [get_ports {passthru_chipset_data_n[28]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[28]}] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[28]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[3]}] +#set_property PACKAGE_PIN G29 [get_ports {chipset_passthru_data_p[3]}] +#set_property PACKAGE_PIN F30 [get_ports {chipset_passthru_data_n[3]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[3]}] +set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[3]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[5]}] +#set_property PACKAGE_PIN G27 [get_ports {chipset_passthru_data_p[5]}] +#set_property PACKAGE_PIN F27 [get_ports {chipset_passthru_data_n[5]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[5]}] +set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[5]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[21]}] +#set_property PACKAGE_PIN G28 [get_ports {chipset_passthru_data_p[21]}] +#set_property PACKAGE_PIN F28 [get_ports {chipset_passthru_data_n[21]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[21]}] +set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[21]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[23]}] +#set_property PACKAGE_PIN D21 [get_ports {chipset_passthru_data_p[23]}] +#set_property PACKAGE_PIN C21 [get_ports {chipset_passthru_data_n[23]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[23]}] +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[23]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[27]}] +#set_property PACKAGE_PIN G18 [get_ports {chipset_passthru_data_p[27]}] +#set_property PACKAGE_PIN F18 [get_ports {chipset_passthru_data_n[27]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[27]}] +set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[27]}] + +#set_property PACKAGE_PIN F13 [get_ports piton_ready_n] +#set_property IOSTANDARD LVCMOS18 [get_ports piton_ready_n] +#set_property PULLUP true [get_ports piton_ready_n] +#set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS18} [get_ports chipset_prsnt_n] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[7]}] +#set_property PACKAGE_PIN H15 [get_ports {chipset_passthru_data_p[7]}] +#set_property PACKAGE_PIN G15 [get_ports {chipset_passthru_data_n[7]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[7]}] +set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[7]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[8]}] +#set_property PACKAGE_PIN L15 [get_ports {chipset_passthru_data_p[8]}] +#set_property PACKAGE_PIN K15 [get_ports {chipset_passthru_data_n[8]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[8]}] +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[8]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_n[4]}] +#set_property PACKAGE_PIN H14 [get_ports {chipset_passthru_data_p[4]}] +#set_property PACKAGE_PIN G14 [get_ports {chipset_passthru_data_n[4]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_data_p[4]}] +set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports {intf_chip_data[4]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[23]}] +#set_property PACKAGE_PIN J16 [get_ports {passthru_chipset_data_p[23]}] +#set_property PACKAGE_PIN H16 [get_ports {passthru_chipset_data_n[23]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[23]}] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[23]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[27]}] +#set_property PACKAGE_PIN L16 [get_ports {passthru_chipset_data_p[27]}] +#set_property PACKAGE_PIN K16 [get_ports {passthru_chipset_data_n[27]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[27]}] +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[27]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[17]}] +#set_property PACKAGE_PIN F12 [get_ports {passthru_chipset_data_p[17]}] +#set_property PACKAGE_PIN E13 [get_ports {passthru_chipset_data_n[17]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[17]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[24]}] +#set_property PACKAGE_PIN B13 [get_ports {passthru_chipset_data_p[24]}] +#set_property PACKAGE_PIN A13 [get_ports {passthru_chipset_data_n[24]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[24]}] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[24]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[26]}] +#set_property PACKAGE_PIN K14 [get_ports {passthru_chipset_data_p[26]}] +#set_property PACKAGE_PIN J14 [get_ports {passthru_chipset_data_n[26]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[26]}] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[26]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[19]}] +#set_property PACKAGE_PIN C15 [get_ports {passthru_chipset_data_p[19]}] +#set_property PACKAGE_PIN B15 [get_ports {passthru_chipset_data_n[19]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[19]}] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[19]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[1]}] +#set_property PACKAGE_PIN J11 [get_ports {passthru_chipset_data_p[1]}] +#set_property PACKAGE_PIN J12 [get_ports {passthru_chipset_data_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[1]}] +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[1]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[12]}] +#set_property PACKAGE_PIN D11 [get_ports {passthru_chipset_data_p[12]}] +#set_property PACKAGE_PIN C11 [get_ports {passthru_chipset_data_n[12]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[12]}] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[12]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[2]}] +#set_property PACKAGE_PIN A11 [get_ports {passthru_chipset_data_p[2]}] +#set_property PACKAGE_PIN A12 [get_ports {passthru_chipset_data_n[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[2]}] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[2]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[4]}] +#set_property PACKAGE_PIN C12 [get_ports {passthru_chipset_data_p[4]}] +#set_property PACKAGE_PIN B12 [get_ports {passthru_chipset_data_n[4]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[4]}] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[4]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[1]}] +#set_property PACKAGE_PIN H11 [get_ports {passthru_chipset_channel_p[1]}] +#set_property PACKAGE_PIN H12 [get_ports {passthru_chipset_channel_n[1]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[1]}] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[1]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[3]}] +#set_property PACKAGE_PIN L12 [get_ports {passthru_chipset_data_p[3]}] +#set_property PACKAGE_PIN L13 [get_ports {passthru_chipset_data_n[3]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[3]}] +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[3]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[0]}] +#set_property PACKAGE_PIN K13 [get_ports {chipset_passthru_credit_back_p[0]}] +#set_property PACKAGE_PIN J13 [get_ports {chipset_passthru_credit_back_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[0]}] +set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[0]}] + + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_n[0]}] +#set_property PACKAGE_PIN D12 [get_ports {passthru_chipset_channel_p[0]}] +#set_property PACKAGE_PIN D13 [get_ports {passthru_chipset_channel_n[0]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_channel_p[0]}] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18} [get_ports {chip_intf_channel[0]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_n[5]}] +#set_property PACKAGE_PIN E14 [get_ports {passthru_chipset_data_p[5]}] +#set_property PACKAGE_PIN E15 [get_ports {passthru_chipset_data_n[5]}] +#set_property IOSTANDARD LVDS_25 [get_ports {passthru_chipset_data_p[5]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports {chip_intf_data[5]}] + +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_n[2]}] +#set_property PACKAGE_PIN E11 [get_ports {chipset_passthru_credit_back_n[2]}] +#set_property PACKAGE_PIN F11 [get_ports {chipset_passthru_credit_back_p[2]}] +#set_property IOSTANDARD LVDS_25 [get_ports {chipset_passthru_credit_back_p[2]}] +set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports {intf_chip_credit_back[2]}] + +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS25 } [get_ports { F78_N }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS25 } [get_ports { F78_P }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS25 } [get_ports { F79_N }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS25 } [get_ports { F79_P }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] + +# ############################################################### +# Input and output delay constraints +# ############################################################### +# Inputs +# Try by saying can arrive in 90% of clock period +# 90% * 125 = 112.5 +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_channel[1]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_channel[0]}] + +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[31]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[30]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[29]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[28]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[27]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[26]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[25]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[24]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[23]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[22]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[21]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[20]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[19]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[18]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[17]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[16]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[15]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[14]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[13]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[12]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[11]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[10]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[9]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[8]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[7]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[6]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[5]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[4]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[3]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[2]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[1]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {chip_intf_data[0]}] + +set_input_delay -clock io_clk -max 112.500 [get_ports {intf_chip_credit_back[2]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {intf_chip_credit_back[1]}] +set_input_delay -clock io_clk -max 112.500 [get_ports {intf_chip_credit_back[0]}] + +# Outputs +# Try by saying can leave in 20% of clock period +# 20% * 125 = 25 + +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_channel[1]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_channel[0]}] + +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[31]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[30]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[29]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[28]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[27]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[26]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[25]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[24]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[23]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[22]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[21]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[20]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[19]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[18]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[17]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[16]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[15]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[14]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[13]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[12]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[11]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[10]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[9]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[8]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[7]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[6]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[5]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[4]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[3]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[2]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[1]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {intf_chip_data[0]}] + +set_output_delay -clock io_clk -max 25.000 [get_ports {chip_intf_credit_back[2]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {chip_intf_credit_back[1]}] +set_output_delay -clock io_clk -max 25.000 [get_ports {chip_intf_credit_back[0]}] ### False paths -set_clock_groups -name sync_gr1 -logically_exclusive -group [get_clocks chipset_clk_clk_mmcm] -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] -set_false_path -from [get_clocks clk_osc_p] -to [get_clocks clk_osc_n] -set_false_path -from [get_clocks clk_osc_n] -to [get_clocks clk_osc_p] +#set_clock_groups -name sync_gr1 -logically_exclusive -group [get_clocks chipset_clk_clk_mmcm] -group [get_clocks -include_generated_clocks mc_sys_clk_clk_mmcm] +#set_false_path -from [get_clocks clk_osc_p] -to [get_clocks clk_osc_n] +#set_false_path -from [get_clocks clk_osc_n] -to [get_clocks clk_osc_p] #set_false_path -from [get_clocks chipset_clk_clk_mmcm] -to [get_clocks chipset_clk_mmcm_1] #set_false_path -from [get_clocks chipset_clk_clk_mmcm_1] -to [get_clocks chipset_clk_clk_mmcm] #set_false_path -from [get_clocks clk_pll_i_1] -to [get_clocks clk_pll_i] @@ -533,37 +820,228 @@ set_false_path -from [get_clocks clk_osc_n] -to [get_clocks clk_osc_p] #set_false_path -from [get_clocks core_ref_clk_clk_mmcm_1] -to [get_clocks clk_pll_i_1] -set_property LOC ILOGIC_X1Y119 [get_cells {chipset_impl/mc_top/mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det/u_phase_detector}] -set_property PACKAGE_PIN AG2 [get_ports {ddr_dqs_p[2]}] -set_property PACKAGE_PIN AH1 [get_ports {ddr_dqs_n[2]}] +#set_property LOC ILOGIC_X1Y119 [get_cells {chipset_impl/mc_top/mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det/u_phase_detector}] +#set_property PACKAGE_PIN AG2 [get_ports {ddr_dqs_p[2]}] +#set_property PACKAGE_PIN AH1 [get_ports {ddr_dqs_n[2]}] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] ############################################# # SD Card Constraints for 25MHz ############################################# -create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] -create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] -create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] -create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] -create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000} -create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000} -set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}] -set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd] -set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd] -set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd] -set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd] -set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd] -set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] -set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}] -set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] +#create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q] +#create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q] +#create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out] +#create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out] +#create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000} +#create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000} +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}] +#set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd] +#set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd] +#set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd] +#set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1] +#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}] +#set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }] + + +#connect_debug_port u_ila_0/probe4 [get_nets [list {chipset_impl/packet_gen_i/data_out[0]} {chipset_impl/packet_gen_i/data_out[1]} {chipset_impl/packet_gen_i/data_out[2]} {chipset_impl/packet_gen_i/data_out[3]} {chipset_impl/packet_gen_i/data_out[4]} {chipset_impl/packet_gen_i/data_out[5]} {chipset_impl/packet_gen_i/data_out[6]} {chipset_impl/packet_gen_i/data_out[7]} {chipset_impl/packet_gen_i/data_out[8]} {chipset_impl/packet_gen_i/data_out[9]} {chipset_impl/packet_gen_i/data_out[10]} {chipset_impl/packet_gen_i/data_out[11]} {chipset_impl/packet_gen_i/data_out[12]} {chipset_impl/packet_gen_i/data_out[13]} {chipset_impl/packet_gen_i/data_out[14]} {chipset_impl/packet_gen_i/data_out[15]} {chipset_impl/packet_gen_i/data_out[16]} {chipset_impl/packet_gen_i/data_out[17]} {chipset_impl/packet_gen_i/data_out[18]} {chipset_impl/packet_gen_i/data_out[19]} {chipset_impl/packet_gen_i/data_out[20]} {chipset_impl/packet_gen_i/data_out[21]} {chipset_impl/packet_gen_i/data_out[22]} {chipset_impl/packet_gen_i/data_out[23]} {chipset_impl/packet_gen_i/data_out[24]} {chipset_impl/packet_gen_i/data_out[25]} {chipset_impl/packet_gen_i/data_out[26]} {chipset_impl/packet_gen_i/data_out[27]} {chipset_impl/packet_gen_i/data_out[28]} {chipset_impl/packet_gen_i/data_out[29]} {chipset_impl/packet_gen_i/data_out[30]} {chipset_impl/packet_gen_i/data_out[31]} {chipset_impl/packet_gen_i/data_out[32]} {chipset_impl/packet_gen_i/data_out[33]} {chipset_impl/packet_gen_i/data_out[34]} {chipset_impl/packet_gen_i/data_out[35]} {chipset_impl/packet_gen_i/data_out[36]} {chipset_impl/packet_gen_i/data_out[37]} {chipset_impl/packet_gen_i/data_out[38]} {chipset_impl/packet_gen_i/data_out[39]} {chipset_impl/packet_gen_i/data_out[40]} {chipset_impl/packet_gen_i/data_out[41]} {chipset_impl/packet_gen_i/data_out[42]} {chipset_impl/packet_gen_i/data_out[43]} {chipset_impl/packet_gen_i/data_out[44]} {chipset_impl/packet_gen_i/data_out[45]} {chipset_impl/packet_gen_i/data_out[46]} {chipset_impl/packet_gen_i/data_out[47]} {chipset_impl/packet_gen_i/data_out[48]} {chipset_impl/packet_gen_i/data_out[49]} {chipset_impl/packet_gen_i/data_out[50]} {chipset_impl/packet_gen_i/data_out[51]} {chipset_impl/packet_gen_i/data_out[52]} {chipset_impl/packet_gen_i/data_out[53]} {chipset_impl/packet_gen_i/data_out[54]} {chipset_impl/packet_gen_i/data_out[55]} {chipset_impl/packet_gen_i/data_out[56]} {chipset_impl/packet_gen_i/data_out[57]} {chipset_impl/packet_gen_i/data_out[58]} {chipset_impl/packet_gen_i/data_out[59]} {chipset_impl/packet_gen_i/data_out[60]} {chipset_impl/packet_gen_i/data_out[61]} {chipset_impl/packet_gen_i/data_out[62]} {chipset_impl/packet_gen_i/data_out[63]}]] +#connect_debug_port u_ila_0/probe5 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc1]] +#connect_debug_port u_ila_0/probe6 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc2]] +#connect_debug_port u_ila_0/probe7 [get_nets [list chipset_impl/packet_gen_i/chipset_intf_rdy_noc3]] +#connect_debug_port u_ila_0/probe8 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc1_valid]] +#connect_debug_port u_ila_0/probe9 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc2_valid]] +#connect_debug_port u_ila_0/probe10 [get_nets [list chipset_impl/packet_gen_i/offchip_processor_noc3_valid]] + +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_36]] +connect_debug_port u_ila_0/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_37]] +connect_debug_port u_ila_0/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_38]] +connect_debug_port u_ila_0/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_39]] + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list clk_mmcm/inst/chipset_clk]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 3 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {fpga_bridge/fpga_chip_out/credit_from_chip_ff[0]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[1]} {fpga_bridge/fpga_chip_out/credit_from_chip_ff[2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 3 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {fpga_bridge/fpga_chip_in/credit_fifo_out[0]} {fpga_bridge/fpga_chip_in/credit_fifo_out[1]} {fpga_bridge/fpga_chip_in/credit_fifo_out[2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 64 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_data[0]} {fpga_bridge/fpga_chip_in/buffered_data[1]} {fpga_bridge/fpga_chip_in/buffered_data[2]} {fpga_bridge/fpga_chip_in/buffered_data[3]} {fpga_bridge/fpga_chip_in/buffered_data[4]} {fpga_bridge/fpga_chip_in/buffered_data[5]} {fpga_bridge/fpga_chip_in/buffered_data[6]} {fpga_bridge/fpga_chip_in/buffered_data[7]} {fpga_bridge/fpga_chip_in/buffered_data[8]} {fpga_bridge/fpga_chip_in/buffered_data[9]} {fpga_bridge/fpga_chip_in/buffered_data[10]} {fpga_bridge/fpga_chip_in/buffered_data[11]} {fpga_bridge/fpga_chip_in/buffered_data[12]} {fpga_bridge/fpga_chip_in/buffered_data[13]} {fpga_bridge/fpga_chip_in/buffered_data[14]} {fpga_bridge/fpga_chip_in/buffered_data[15]} {fpga_bridge/fpga_chip_in/buffered_data[16]} {fpga_bridge/fpga_chip_in/buffered_data[17]} {fpga_bridge/fpga_chip_in/buffered_data[18]} {fpga_bridge/fpga_chip_in/buffered_data[19]} {fpga_bridge/fpga_chip_in/buffered_data[20]} {fpga_bridge/fpga_chip_in/buffered_data[21]} {fpga_bridge/fpga_chip_in/buffered_data[22]} {fpga_bridge/fpga_chip_in/buffered_data[23]} {fpga_bridge/fpga_chip_in/buffered_data[24]} {fpga_bridge/fpga_chip_in/buffered_data[25]} {fpga_bridge/fpga_chip_in/buffered_data[26]} {fpga_bridge/fpga_chip_in/buffered_data[27]} {fpga_bridge/fpga_chip_in/buffered_data[28]} {fpga_bridge/fpga_chip_in/buffered_data[29]} {fpga_bridge/fpga_chip_in/buffered_data[30]} {fpga_bridge/fpga_chip_in/buffered_data[31]} {fpga_bridge/fpga_chip_in/buffered_data[32]} {fpga_bridge/fpga_chip_in/buffered_data[33]} {fpga_bridge/fpga_chip_in/buffered_data[34]} {fpga_bridge/fpga_chip_in/buffered_data[35]} {fpga_bridge/fpga_chip_in/buffered_data[36]} {fpga_bridge/fpga_chip_in/buffered_data[37]} {fpga_bridge/fpga_chip_in/buffered_data[38]} {fpga_bridge/fpga_chip_in/buffered_data[39]} {fpga_bridge/fpga_chip_in/buffered_data[40]} {fpga_bridge/fpga_chip_in/buffered_data[41]} {fpga_bridge/fpga_chip_in/buffered_data[42]} {fpga_bridge/fpga_chip_in/buffered_data[43]} {fpga_bridge/fpga_chip_in/buffered_data[44]} {fpga_bridge/fpga_chip_in/buffered_data[45]} {fpga_bridge/fpga_chip_in/buffered_data[46]} {fpga_bridge/fpga_chip_in/buffered_data[47]} {fpga_bridge/fpga_chip_in/buffered_data[48]} {fpga_bridge/fpga_chip_in/buffered_data[49]} {fpga_bridge/fpga_chip_in/buffered_data[50]} {fpga_bridge/fpga_chip_in/buffered_data[51]} {fpga_bridge/fpga_chip_in/buffered_data[52]} {fpga_bridge/fpga_chip_in/buffered_data[53]} {fpga_bridge/fpga_chip_in/buffered_data[54]} {fpga_bridge/fpga_chip_in/buffered_data[55]} {fpga_bridge/fpga_chip_in/buffered_data[56]} {fpga_bridge/fpga_chip_in/buffered_data[57]} {fpga_bridge/fpga_chip_in/buffered_data[58]} {fpga_bridge/fpga_chip_in/buffered_data[59]} {fpga_bridge/fpga_chip_in/buffered_data[60]} {fpga_bridge/fpga_chip_in/buffered_data[61]} {fpga_bridge/fpga_chip_in/buffered_data[62]} {fpga_bridge/fpga_chip_in/buffered_data[63]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 2 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {fpga_bridge/fpga_chip_in/buffered_channel[0]} {fpga_bridge/fpga_chip_in/buffered_channel[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[0]_i_1_n_0}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {fpga_bridge/fpga_chip_out/serial_buffer_channel[1]_i_1_n_0}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 1 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_24]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_25]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_26]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_27]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_28]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +set_property port_width 1 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_29]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +set_property port_width 1 [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_30]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 1 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_31]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_32]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_33]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_34]] +create_debug_core u_ila_1 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1] +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_1] +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] +set_property port_width 1 [get_debug_ports u_ila_1/clk] +connect_debug_port u_ila_1/clk [get_nets [list not_intf_out_clk]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] +set_property port_width 1 [get_debug_ports u_ila_1/probe0] +connect_debug_port u_ila_1/probe0 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_3]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] +set_property port_width 1 [get_debug_ports u_ila_1/probe1] +connect_debug_port u_ila_1/probe1 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_4]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] +set_property port_width 1 [get_debug_ports u_ila_1/probe2] +connect_debug_port u_ila_1/probe2 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_5]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] +set_property port_width 1 [get_debug_ports u_ila_1/probe3] +connect_debug_port u_ila_1/probe3 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_6]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4] +set_property port_width 1 [get_debug_ports u_ila_1/probe4] +connect_debug_port u_ila_1/probe4 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_7]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5] +set_property port_width 1 [get_debug_ports u_ila_1/probe5] +connect_debug_port u_ila_1/probe5 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_8]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6] +set_property port_width 1 [get_debug_ports u_ila_1/probe6] +connect_debug_port u_ila_1/probe6 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_9]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7] +set_property port_width 1 [get_debug_ports u_ila_1/probe7] +connect_debug_port u_ila_1/probe7 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_10]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8] +set_property port_width 1 [get_debug_ports u_ila_1/probe8] +connect_debug_port u_ila_1/probe8 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_11]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9] +set_property port_width 1 [get_debug_ports u_ila_1/probe9] +connect_debug_port u_ila_1/probe9 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_12]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10] +set_property port_width 1 [get_debug_ports u_ila_1/probe10] +connect_debug_port u_ila_1/probe10 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_13]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11] +set_property port_width 1 [get_debug_ports u_ila_1/probe11] +connect_debug_port u_ila_1/probe11 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_14]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12] +set_property port_width 1 [get_debug_ports u_ila_1/probe12] +connect_debug_port u_ila_1/probe12 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_15]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13] +set_property port_width 1 [get_debug_ports u_ila_1/probe13] +connect_debug_port u_ila_1/probe13 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_16]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14] +set_property port_width 1 [get_debug_ports u_ila_1/probe14] +connect_debug_port u_ila_1/probe14 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_17]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15] +set_property port_width 1 [get_debug_ports u_ila_1/probe15] +connect_debug_port u_ila_1/probe15 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_18]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16] +set_property port_width 1 [get_debug_ports u_ila_1/probe16] +connect_debug_port u_ila_1/probe16 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_19]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17] +set_property port_width 1 [get_debug_ports u_ila_1/probe17] +connect_debug_port u_ila_1/probe17 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_20]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18] +set_property port_width 1 [get_debug_ports u_ila_1/probe18] +connect_debug_port u_ila_1/probe18 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_21]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe19] +set_property port_width 1 [get_debug_ports u_ila_1/probe19] +connect_debug_port u_ila_1/probe19 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_22]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe20] +set_property port_width 1 [get_debug_ports u_ila_1/probe20] +connect_debug_port u_ila_1/probe20 [get_nets [list fpga_bridge/fpga_chip_out/separator_n_23]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets dbg2_OBUF] diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci index 454104a47..17e74af9b 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/afifo_w64_d128_std/afifo_w64_d128_std.xci @@ -7,13 +7,129 @@ afifo_w64_d128_std - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,28 +501,58 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -420,6 +566,14 @@ + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci index 5cb30b834..8a7755f96 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm/clk_mmcm.xci @@ -7,13 +7,118 @@ clk_mmcm - + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 MMCM cddcdone cddcreq 0000 - 0080 + 0000 clkfb_in_n clkfb_in clkfb_in_p @@ -24,80 +129,80 @@ clkfb_stopped 50.0 100.0 - 1105 - 0080 - 66.667 - 1042 - 0080 - 200.000 + 0000 + 0000 + 8.00000 + 0000 + 0000 + 200.00000 BUFG 50.0 false - 66.667 + 8.00000 0.000 50.000 - 66.666 + 8 0.000 1 - 1186 + 0000 0000 - 50.000 + 8.00000 BUFG 50.0 false - 200.000 + 200.00000 0.000 50.000 200.000 0.000 1 1 - 10c3 + 0000 0000 - 100.000 + 8.00000 BUFG 50.0 false - 50.000 + 8.00000 0.000 50.000 - 50.000 + 8 0.000 1 1 - 10c3 - 0003 - 100.000 + 0000 + 0000 + 100.00000 BUFG 50.0 false - 100.000 - 0.000 + 8.00000 + 180.000 50.000 - 100.000 - 0.000 + 8 + 180.000 1 1 - 130c + 0000 0000 - 25.000 + 25.00000 BUFG 50.0 false - 100.000 + 100.00000 180.000 50.000 100.000 180.000 1 1 - 10c3 - 0080 - 100.000 + 0000 + 0000 + 100.00000 BUFG 50.0 false - 25.000 + 25.00000 0.000 50.000 25.000 @@ -107,7 +212,7 @@ BUFG 50.0 false - 100.000 + 100.00000 0.000 50.000 100.000 @@ -118,8 +223,8 @@ clk_in_sel chipset_clk mc_sys_clk - sd_sys_clk - chipset_passthru_clk + io_clk + io_clk_not chipset_passthru_clk_n net_phy_clk net_axi_clk @@ -129,17 +234,19 @@ dclk den din - 1041 + 0000 1 - 0.33332999999999996 - 1.3333199999999998 - 0.6666599999999999 - 0.6666599999999999 - 2.6666399999999997 - 0.6666599999999999 + 0.04 + 1.0 + 1.0 + 0.08 + 0.32 + 0.08 dout drdy dwe + 93.000 + 1.000 0 0 0 @@ -149,8 +256,8 @@ 0 0 FDBK_AUTO - 0800 - 9990 + 0000 + 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________200.000____________0.010 @@ -160,9 +267,9 @@ Units_MHz No_Jitter locked - 03e8 - 2001 - 23e9 + 0000 + 0000 + 0000 false false false @@ -172,37 +279,37 @@ false false OPTIMIZED - 3.000 + 5.000 0.000 FALSE - 5.0 + 5.000 10.0 - 9.000 + 125.000 0.500 0.000 FALSE - 3 + 5 0.500 0.000 FALSE - 12 + 125 0.500 0.000 FALSE - 6 + 125 0.500 - 0.000 + 180.000 FALSE FALSE - 6 + 10 0.500 180.000 FALSE - 24 + 40 0.500 0.000 FALSE - 6 + 10 0.500 0.000 FALSE @@ -213,18 +320,23 @@ 0.010 0.010 FALSE + 64.000 + 2.000 7 + 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - chipset_clk____66.667______0.000______50.0______117.498____105.563 - mc_sys_clk___200.000______0.000______50.0_______94.528____105.563 - sd_sys_clk____50.000______0.000______50.0______124.683____105.563 - chipset_passthru_clk___100.000______0.000______50.0______108.247____105.563 - chipset_passthru_clk_n___100.000____180.000______50.0______108.247____105.563 - net_phy_clk____25.000______0.000______50.0______143.534____105.563 - net_axi_clk___100.000______0.000______50.0______108.247____105.563 + chipset_clk___8.00000______0.000______50.0______186.029_____89.971 + mc_sys_clk__200.00000______0.000______50.0_______98.146_____89.971 + __io_clk___8.00000______0.000______50.0______186.029_____89.971 + io_clk_not___8.00000____180.000______50.0______186.029_____89.971 + chipset_passthru_clk_n__100.00000____180.000______50.0______112.316_____89.971 + net_phy_clk__25.00000______0.000______50.0______148.629_____89.971 + net_axi_clk__100.00000______0.000______50.0______112.316_____89.971 0 0 + 128.000 + 1.000 WAVEFORM UNKNOWN false @@ -260,7 +372,7 @@ No notes 0.010 power_down - FFFF + 0000 1 clk_in1 MMCM @@ -315,6 +427,8 @@ 0 0 0 + 1440.000 + 600.000 clk_mmcm MMCM false @@ -334,63 +448,63 @@ 100.0 0.010 BUFG - 117.498 + 186.029 false - 105.563 + 89.971 50.000 - 66.666 + 8 0.000 1 true BUFG - 94.528 + 98.146 false - 105.563 + 89.971 50.000 200.000 0.000 1 true BUFG - 124.683 + 186.029 false - 105.563 + 89.971 50.000 - 50.000 + 8 0.000 1 true BUFG - 108.247 + 186.029 false - 105.563 + 89.971 50.000 - 100.000 - 0.000 + 8 + 180.000 1 true BUFG - 108.247 + 112.316 false - 105.563 + 89.971 50.000 100.000 180.000 1 true BUFG - 143.534 + 148.629 false - 105.563 + 89.971 50.000 25.000 0.000 1 true BUFG - 108.247 + 112.316 false - 105.563 + 89.971 50.000 100.000 0.000 @@ -404,9 +518,9 @@ false mc_sys_clk false - sd_sys_clk + io_clk false - chipset_passthru_clk + io_clk_not false chipset_passthru_clk_n false @@ -445,37 +559,37 @@ No_Jitter locked OPTIMIZED - 3.000 + 5.000 0.000 false - 5.0 + 5.000 10.0 - 9.000 + 125.000 0.500 0.000 false - 3 + 5 0.500 0.000 false - 12 + 125 0.500 0.000 false - 6 + 125 0.500 - 0.000 + 180.000 false false - 6 + 10 0.500 180.000 false - 24 + 40 0.500 0.000 false - 6 + 10 0.500 0.000 false @@ -487,6 +601,7 @@ 0.010 false 7 + false false false WAVEFORM @@ -572,28 +687,48 @@ false false kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 8 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + @@ -610,6 +745,7 @@ + @@ -618,19 +754,26 @@ + + + + + + + @@ -642,6 +785,23 @@ + + + diff --git a/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci b/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci index 8ec9fc732..b4210bd91 100644 --- a/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci +++ b/piton/design/chipset/xilinx/genesys2/ip_cores/mac_eth_axi_lite/mac_eth_axi_lite.xci @@ -9,6 +9,45 @@ mac_eth_axi_lite + 1 + false + 13 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0.0 + 0 1 kintex7 1 @@ -37,25 +76,74 @@ Custom false kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 9 + 23 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci b/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci index 947f56ca8..d5cfb8351 100644 --- a/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci +++ b/piton/design/common/fpga_bridge/common/xilinx/genesys2/ip_cores/afifo_w64/afifo_w64.xci @@ -7,13 +7,129 @@ afifo_w64 - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,29 +501,59 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -427,6 +573,14 @@ + + + diff --git a/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci b/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci index 57d7873d8..68a373b0c 100644 --- a/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci +++ b/piton/design/common/fpga_bridge/fpga_rcv/xilinx/genesys2/ip_cores/afifo_w3/afifo_w3.xci @@ -7,13 +7,129 @@ afifo_w3 - + + + + 100000000 + 0 + 0 + 0.0 + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 0 0 0 @@ -385,29 +501,59 @@ FIFO FIFO kintex7 - + digilentinc.com:genesys2:part0:1.1 + xc7k325t ffg900 VERILOG MIXED -2 + TRUE TRUE IP_Flow - 3 + 5 TRUE . . - 2016.4 + 2021.1 OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -427,6 +573,14 @@ + + + diff --git a/piton/design/common/fpga_bridge/rtl/fpga_bridge.v b/piton/design/common/fpga_bridge/rtl/fpga_bridge.v index 032616756..fefaa9976 100644 --- a/piton/design/common/fpga_bridge/rtl/fpga_bridge.v +++ b/piton/design/common/fpga_bridge/rtl/fpga_bridge.v @@ -72,12 +72,15 @@ module fpga_bridge( parameter SEND_CREDIT_THRESHOLD = 9'd255; + wire not_intf_out_clk = ~intf_out_clk; + + fpga_bridge_send_32 #( .FULL_THRESHOLD(SEND_CREDIT_THRESHOLD) )fpga_chip_out( .rst(~rst_n), .wr_clk(fpga_out_clk), - .rd_clk(intf_out_clk), + .rd_clk(not_intf_out_clk), .credit_wr_clk(intf_in_clk), .bin_data_1(fpga_intf_data_noc1), .bin_val_1(fpga_intf_val_noc1), @@ -97,7 +100,7 @@ fpga_bridge_rcv_32 fpga_chip_in ( .rst(~rst_n), .wr_clk(intf_in_clk), .rd_clk(fpga_in_clk), - .credit_rd_clk(intf_out_clk), + .credit_rd_clk(not_intf_out_clk), .bout_data_1(intf_fpga_data_noc1), .bout_val_1(intf_fpga_val_noc1), .bout_rdy_1(intf_fpga_rdy_noc1), diff --git a/piton/design/common/rtl/bram_1r1w_wrapper.v b/piton/design/common/rtl/bram_1r1w_wrapper.v index 73ddcbe45..210db1dce 100644 --- a/piton/design/common/rtl/bram_1r1w_wrapper.v +++ b/piton/design/common/rtl/bram_1r1w_wrapper.v @@ -115,6 +115,7 @@ always @ * begin // note: DOUT retains value if read enable is not asserted // which is why default value is not set for DOUT + DOUTA=0; // default value if (read_enable_in_reg) begin DOUTA = bram_data_read_out_reg; if (rw_conflict_r) begin diff --git a/piton/design/include/piton_system.vh b/piton/design/include/piton_system.vh index 5b6618fd8..0c25e8f71 100644 --- a/piton/design/include/piton_system.vh +++ b/piton/design/include/piton_system.vh @@ -122,6 +122,8 @@ `define PITON_CHIPSET_DIFF_CLK `elsif GENESYS2_BOARD `define PITON_CHIPSET_DIFF_CLK +`elsif ALVEO_BOARD + `define PITON_CHIPSET_DIFF_CLK `elsif PITON_BOARD `define PITON_CHIPSET_DIFF_CLK `define PITON_CHIPSET_DIFF_CLK_POLARITY_CAPS @@ -134,6 +136,8 @@ `define PITON_FPGA_RST_ACT_HIGH `elsif VCU118_BOARD `define PITON_FPGA_RST_ACT_HIGH +`elsif ALVEO_BOARD + `define PITON_FPGA_RST_ACT_HIGH `endif `ifdef XUPP3R_BOARD @@ -143,6 +147,9 @@ `undef PITON_FPGA_SD_BOOT `undef PITONSYS_SPI `define PITONSYS_AXI4_MEM +`elsif ALVEO_BOARD + `undef PITON_FPGA_SD_BOOT + `undef PITONSYS_SPI `endif // If PITON_FPGA_SD_BOOT is set we should always include SPI @@ -159,4 +166,12 @@ `define PITONSYS_DDR4 `elsif XUPP3R_BOARD `define PITONSYS_DDR4 +`elsif ALVEO_BOARD + `define PITONSYS_DDR4 `endif + +`ifdef XUPP3R_BOARD + `define XUPP3R_OR_ALVEO +`elsif ALVEO_BOARD + `define XUPP3R_OR_ALVEO +`endif \ No newline at end of file diff --git a/piton/design/rtl/system.v b/piton/design/rtl/system.v index 48362dfdf..732d4448d 100644 --- a/piton/design/rtl/system.v +++ b/piton/design/rtl/system.v @@ -112,6 +112,17 @@ module system( input passthru_chipset_clk_n, `endif // endif PITON_PASSTHRU_CLKS_GEN `endif // endif PITON_SYS_INC_PASSTHRU + +`ifdef ALVEO_BOARD + input pcie_refclk_clk_n , + input pcie_refclk_clk_p , + input pcie_perstn , + input [15:0] pci_express_x16_rxn , + input [15:0] pci_express_x16_rxp , + output [15:0] pci_express_x16_txn , + output [15:0] pci_express_x16_txp , + input resetn , +`endif `ifndef F1_BOARD `ifdef PITON_CHIPSET_CLKS_GEN @@ -147,7 +158,9 @@ module system( input sys_clk, `endif +`ifndef ALVEO_BOARD input sys_rst_n, +`endif `ifndef PITON_FPGA_SYNTH input fll_rst_n, @@ -188,6 +201,7 @@ module system( `ifndef VCU118_BOARD `ifndef NEXYSVIDEO_BOARD `ifndef XUPP3R_BOARD +`ifndef ALVEO_BOARD `ifndef F1_BOARD input tck_i, input tms_i, @@ -195,6 +209,7 @@ module system( input td_i, output td_o, `endif//F1_BOARD +`endif //ALVEO_BOARD `endif//XUPP3R_BOARD `endif //NEXYSVIDEO_BOARD `endif //VCU118_BOARD @@ -238,11 +253,11 @@ module system( output [`DDR3_CS_WIDTH-1:0] ddr_cs_n, `endif // endif NEXYSVIDEO_BOARD `ifdef PITONSYS_DDR4 - `ifdef XUPP3R_BOARD + `ifdef XUPP3R_OR_ALVEO output ddr_parity, `else inout [`DDR3_DM_WIDTH-1:0] ddr_dm, - `endif // XUPP3R_BOARD + `endif // XUPP3R_OR_ALVEO `else // PITONSYS_DDR4 output [`DDR3_DM_WIDTH-1:0] ddr_dm, `endif // PITONSYS_DDR4 @@ -392,7 +407,7 @@ module system( `ifdef VCU118_BOARD // we only have 4 gpio dip switches on this board input [3:0] sw, -`elsif XUPP3R_BOARD +`elsif XUPP3R_OR_ALVEO // no switches :( `else input [7:0] sw, @@ -400,6 +415,8 @@ module system( `ifdef XUPP3R_BOARD output [3:0] leds +`elsif ALVEO_BOARD + output hbm_cattrip `else output [7:0] leds `endif @@ -528,6 +545,13 @@ wire uart_rst_out_n; assign uart_rts = 1'b0; `endif // VCU118_BOARD +`ifdef ALVEO_BOARD + + wire sys_rst_n; + assign hbm_cattrip = 1'b0; + +`endif + // Different reset active levels for different boards always @ * begin @@ -991,6 +1015,17 @@ chipset chipset( .mc_clk_n(mc_clk_n), `endif // PITONSYS_DDR4 +`ifdef ALVEO_BOARD + .pcie_refclk_clk_n (pcie_refclk_clk_n) , + .pcie_refclk_clk_p (pcie_refclk_clk_p) , + .pcie_perstn (pcie_perstn) , + .pci_express_x16_rxn (pci_express_x16_rxn) , + .pci_express_x16_rxp (pci_express_x16_rxp) , + .pci_express_x16_txn (pci_express_x16_txn ) , + .pci_express_x16_txp (pci_express_x16_txp) , + .resetn (resetn), +`endif + `else // ifndef PITON_CHIPSET_CLKS_GEN .chipset_clk(chipset_clk), `ifndef PITONSYS_NO_MC @@ -1112,7 +1147,7 @@ chipset chipset( `ifndef NEXYSVIDEO_BOARD .ddr_cs_n(ddr_cs_n), `endif // endif NEXYSVIDEO_BOARD -`ifdef XUPP3R_BOARD +`ifdef XUPP3R_OR_ALVEO .ddr_parity(ddr_parity), `else .ddr_dm(ddr_dm), @@ -1180,6 +1215,10 @@ chipset chipset( `endif // PITON_FPGA_MC_DDR3 `endif // endif PITONSYS_NO_MC +`ifdef ALVEO_BOARD + .chip_rstn (sys_rst_n), +`endif + `ifdef PITONSYS_IOCTRL `ifdef PITONSYS_UART .uart_tx(uart_tx), @@ -1249,7 +1288,7 @@ chipset chipset( .btnc(btnc), `endif -`ifndef XUPP3R_BOARD +`ifndef XUPP3R_OR_ALVEO .sw(sw), `endif .leds(leds) diff --git a/piton/design/xilinx/alveou280/constraints.xdc b/piton/design/xilinx/alveou280/constraints.xdc new file mode 100644 index 000000000..19e29b9f3 --- /dev/null +++ b/piton/design/xilinx/alveou280/constraints.xdc @@ -0,0 +1,281 @@ +# Bitstream generation +# --------------------------------------------------------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +#set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] ;# Customer can try but may not be reliable over all conditions. +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# --------------------------------------------------------------------- + +# Don't time the GPIO reset signals +set_false_path -from [get_pins -hier *Not_Dual.gpio_Data_Out_reg*/C] + +# 156.25MHz General purpose system clock +set_property PACKAGE_PIN BH6 [get_ports chipset_clk_osc_p] +set_property PACKAGE_PIN BJ6 [get_ports chipset_clk_osc_n] +set_property IOSTANDARD LVDS [get_ports chipset_clk*] + +# Reset, connects SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller +set_property PACKAGE_PIN L30 [get_ports resetn] +set_property IOSTANDARD LVCMOS18 [get_ports resetn] + +# UART +set_property PACKAGE_PIN A28 [get_ports uart_rx] +set_property PACKAGE_PIN B33 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_*] + +# PCIe MGTY Interface +set_property PACKAGE_PIN BH26 [get_ports pcie_perstn] +set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] + +set_property PACKAGE_PIN BC2 [get_ports {pci_express_x16_rxp[15]}] +set_property PACKAGE_PIN BC1 [get_ports {pci_express_x16_rxn[15]}] +set_property PACKAGE_PIN BC7 [get_ports {pci_express_x16_txp[15]}] +set_property PACKAGE_PIN BC6 [get_ports {pci_express_x16_txn[15]}] +set_property PACKAGE_PIN BB4 [get_ports {pci_express_x16_rxp[14]}] +set_property PACKAGE_PIN BB3 [get_ports {pci_express_x16_rxn[14]}] +set_property PACKAGE_PIN BC11 [get_ports {pci_express_x16_txp[14]}] +set_property PACKAGE_PIN BC10 [get_ports {pci_express_x16_txn[14]}] +set_property PACKAGE_PIN BA2 [get_ports {pci_express_x16_rxp[13]}] +set_property PACKAGE_PIN BA1 [get_ports {pci_express_x16_rxn[13]}] +set_property PACKAGE_PIN BB9 [get_ports {pci_express_x16_txp[13]}] +set_property PACKAGE_PIN BB8 [get_ports {pci_express_x16_txn[13]}] +set_property PACKAGE_PIN BA6 [get_ports {pci_express_x16_rxp[12]}] +set_property PACKAGE_PIN BA5 [get_ports {pci_express_x16_rxn[12]}] +set_property PACKAGE_PIN BA11 [get_ports {pci_express_x16_txp[12]}] +set_property PACKAGE_PIN BA10 [get_ports {pci_express_x16_txn[12]}] +# Clock +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n] +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p] + +set_property PACKAGE_PIN AY4 [get_ports {pci_express_x16_rxp[11]}] +set_property PACKAGE_PIN AY3 [get_ports {pci_express_x16_rxn[11]}] +set_property PACKAGE_PIN AY9 [get_ports {pci_express_x16_txp[11]}] +set_property PACKAGE_PIN AY8 [get_ports {pci_express_x16_txn[11]}] +set_property PACKAGE_PIN AW2 [get_ports {pci_express_x16_rxp[10]}] +set_property PACKAGE_PIN AW1 [get_ports {pci_express_x16_rxn[10]}] +set_property PACKAGE_PIN AW11 [get_ports {pci_express_x16_txp[10]}] +set_property PACKAGE_PIN AW10 [get_ports {pci_express_x16_txn[10]}] +set_property PACKAGE_PIN AW6 [get_ports {pci_express_x16_rxp[9]}] +set_property PACKAGE_PIN AW5 [get_ports {pci_express_x16_rxn[9]}] +set_property PACKAGE_PIN AV9 [get_ports {pci_express_x16_txp[9]}] +set_property PACKAGE_PIN AV8 [get_ports {pci_express_x16_txn[9]}] +set_property PACKAGE_PIN AV4 [get_ports {pci_express_x16_rxp[8]}] +set_property PACKAGE_PIN AV3 [get_ports {pci_express_x16_rxn[8]}] +set_property PACKAGE_PIN AU7 [get_ports {pci_express_x16_txp[8]}] +set_property PACKAGE_PIN AU6 [get_ports {pci_express_x16_txn[8]}] +set_property PACKAGE_PIN AU2 [get_ports {pci_express_x16_rxp[7]}] +set_property PACKAGE_PIN AU1 [get_ports {pci_express_x16_rxn[7]}] +set_property PACKAGE_PIN AU11 [get_ports {pci_express_x16_txp[7]}] +set_property PACKAGE_PIN AU10 [get_ports {pci_express_x16_txn[7]}] +set_property PACKAGE_PIN AT4 [get_ports {pci_express_x16_rxp[6]}] +set_property PACKAGE_PIN AT3 [get_ports {pci_express_x16_rxn[6]}] +set_property PACKAGE_PIN AT9 [get_ports {pci_express_x16_txp[6]}] +set_property PACKAGE_PIN AT8 [get_ports {pci_express_x16_txn[6]}] +set_property PACKAGE_PIN AR2 [get_ports {pci_express_x16_rxp[5]}] +set_property PACKAGE_PIN AR1 [get_ports {pci_express_x16_rxn[5]}] +set_property PACKAGE_PIN AR7 [get_ports {pci_express_x16_txp[5]}] +set_property PACKAGE_PIN AR6 [get_ports {pci_express_x16_txn[5]}] +set_property PACKAGE_PIN AP4 [get_ports {pci_express_x16_rxp[4]}] +set_property PACKAGE_PIN AP3 [get_ports {pci_express_x16_rxn[4]}] +set_property PACKAGE_PIN AR11 [get_ports {pci_express_x16_txp[4]}] +set_property PACKAGE_PIN AR10 [get_ports {pci_express_x16_txn[4]}] +#set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 +set_property PACKAGE_PIN AN2 [get_ports {pci_express_x16_rxp[3]}] +set_property PACKAGE_PIN AN1 [get_ports {pci_express_x16_rxn[3]}] +set_property PACKAGE_PIN AP9 [get_ports {pci_express_x16_txp[3]}] +set_property PACKAGE_PIN AP8 [get_ports {pci_express_x16_txn[3]}] +set_property PACKAGE_PIN AN6 [get_ports {pci_express_x16_rxp[2]}] +set_property PACKAGE_PIN AN5 [get_ports {pci_express_x16_rxn[2]}] +set_property PACKAGE_PIN AN11 [get_ports {pci_express_x16_txp[2]}] +set_property PACKAGE_PIN AN10 [get_ports {pci_express_x16_txn[2]}] +set_property PACKAGE_PIN AM4 [get_ports {pci_express_x16_rxp[1]}] +set_property PACKAGE_PIN AM3 [get_ports {pci_express_x16_rxn[1]}] +set_property PACKAGE_PIN AM9 [get_ports {pci_express_x16_txp[1]}] +set_property PACKAGE_PIN AM8 [get_ports {pci_express_x16_txn[1]}] +set_property PACKAGE_PIN AL2 [get_ports {pci_express_x16_rxp[0]}] +set_property PACKAGE_PIN AL1 [get_ports {pci_express_x16_rxn[0]}] +set_property PACKAGE_PIN AL11 [get_ports {pci_express_x16_txp[0]}] +set_property PACKAGE_PIN AL10 [get_ports {pci_express_x16_txn[0]}] + +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] + + + + +# 100MHz DDR0 System clock +set_property PACKAGE_PIN BJ43 [get_ports mc_clk_p] +set_property PACKAGE_PIN BJ44 [get_ports mc_clk_n] + + +# DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank +# <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# +set_property -dict {PACKAGE_PIN BH44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[16]}] +set_property -dict {PACKAGE_PIN BL46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[15]}] +#set_property -dict {PACKAGE_PIN BE46 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property -dict {PACKAGE_PIN BK44 IOSTANDARD SSTL12_DCI} [ get_ports {#NA} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 +set_property -dict {PACKAGE_PIN BK46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cs_n[0]}] +set_property -dict {PACKAGE_PIN BE44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[13]}] +#set_property -dict {PACKAGE_PIN BL47 IOSTANDARD SSTL12_DCI} [ get_ports {ddr_addr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +set_property -dict {PACKAGE_PIN BE43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[14]}] +set_property -dict {PACKAGE_PIN BG44 IOSTANDARD SSTL12_DCI} [get_ports {ddr_odt[0]}] +#set_property -dict {PACKAGE_PIN BE45 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property -dict {PACKAGE_PIN BD42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +set_property -dict {PACKAGE_PIN BH45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[0]}] +set_property -dict {PACKAGE_PIN BG45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[10]}] +set_property -dict {PACKAGE_PIN BJ46 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_n[0]}] +set_property -dict {PACKAGE_PIN BH46 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr_ck_p[0]}] +#set_property -dict {PACKAGE_PIN BK41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property -dict {PACKAGE_PIN BJ41 IOSTANDARD DIFF_SSTL12_DCI} [ get_ports {ddr_ck_p[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +set_property -dict {PACKAGE_PIN BM47 IOSTANDARD SSTL12_DCI} [get_ports {ddr_ba[1]}] +set_property -dict {PACKAGE_PIN BF45 IOSTANDARD SSTL12_DCI} [get_ports ddr_parity] +set_property -dict {PACKAGE_PIN BF46 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[0]}] +set_property -dict {PACKAGE_PIN BK45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[2]}] +set_property -dict {PACKAGE_PIN BG43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[1]}] +set_property -dict {PACKAGE_PIN BL45 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[4]}] +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[3]}] +#set_property -dict {PACKAGE_PIN BC42 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 +set_property -dict {PACKAGE_PIN BK43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[8]}] +set_property -dict {PACKAGE_PIN BL43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[7]}] +set_property -dict {PACKAGE_PIN BD41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[11]}] +set_property -dict {PACKAGE_PIN BM42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[9]}] +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[5]}] +set_property -dict {PACKAGE_PIN BG42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[6]}] +#set_property -dict {PACKAGE_PIN BJ42 IOSTANDARD SSTL12_DCI} [ get_ports {c0_ddr4_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +set_property -dict {PACKAGE_PIN BE41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[1]}] +set_property -dict {PACKAGE_PIN BL42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_addr[12]}] +set_property -dict {PACKAGE_PIN BH41 IOSTANDARD SSTL12_DCI} [get_ports ddr_act_n] +set_property -dict {PACKAGE_PIN BH42 IOSTANDARD SSTL12_DCI} [get_ports {ddr_cke[0]}] +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD SSTL12_DCI} [get_ports {ddr_bg[0]}] +set_property -dict {PACKAGE_PIN BE53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[66]}] +set_property -dict {PACKAGE_PIN BE54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[67]}] +set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[16]}] +set_property -dict {PACKAGE_PIN BH54 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[16]}] +set_property -dict {PACKAGE_PIN BG54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[64]}] +set_property -dict {PACKAGE_PIN BG53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[65]}] +set_property -dict {PACKAGE_PIN BK53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[71]}] +set_property -dict {PACKAGE_PIN BK54 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[70]}] +set_property -dict {PACKAGE_PIN BH52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[68]}] +set_property -dict {PACKAGE_PIN BG52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[69]}] +set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[17]}] +set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[17]}] +set_property -dict {PACKAGE_PIN BL52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[34]}] +set_property -dict {PACKAGE_PIN BL51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[35]}] +set_property -dict {PACKAGE_PIN BM50 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[8]}] +set_property -dict {PACKAGE_PIN BM49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[8]}] +#set_property -dict {PACKAGE_PIN BK29 IOSTANDARD LVCMOS12} [ get_ports {c0_ddr4_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 +set_property -dict {PACKAGE_PIN BL53 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[33]}] +set_property -dict {PACKAGE_PIN BM52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[32]}] +set_property -dict {PACKAGE_PIN BN49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[38]}] +set_property -dict {PACKAGE_PIN BM48 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[39]}] +set_property -dict {PACKAGE_PIN BN51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[37]}] +set_property -dict {PACKAGE_PIN BN50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[36]}] +set_property -dict {PACKAGE_PIN BP49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[9]}] +set_property -dict {PACKAGE_PIN BP48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[9]}] +set_property -dict {PACKAGE_PIN BH35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[25]}] +set_property -dict {PACKAGE_PIN BH34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[24]}] +set_property -dict {PACKAGE_PIN BK35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[6]}] +set_property -dict {PACKAGE_PIN BK34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[6]}] +set_property -dict {PACKAGE_PIN BG33 IOSTANDARD LVCMOS12} [get_ports ddr_reset_n] +set_property -dict {PACKAGE_PIN BF36 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[27]}] +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[26]}] +set_property -dict {PACKAGE_PIN BJ34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[29]}] +set_property -dict {PACKAGE_PIN BJ33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[28]}] +set_property -dict {PACKAGE_PIN BG34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[30]}] +set_property -dict {PACKAGE_PIN BG35 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[31]}] +set_property -dict {PACKAGE_PIN BJ32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[7]}] +set_property -dict {PACKAGE_PIN BH32 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[7]}] +set_property -dict {PACKAGE_PIN BL31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[17]}] +set_property -dict {PACKAGE_PIN BK31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[16]}] +set_property -dict {PACKAGE_PIN BM35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[4]}] +set_property -dict {PACKAGE_PIN BL35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[4]}] +set_property -dict {PACKAGE_PIN BL33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[19]}] +set_property -dict {PACKAGE_PIN BK33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[18]}] +set_property -dict {PACKAGE_PIN BM33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[21]}] +set_property -dict {PACKAGE_PIN BL32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[20]}] +set_property -dict {PACKAGE_PIN BP34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[23]}] +set_property -dict {PACKAGE_PIN BN34 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[22]}] +set_property -dict {PACKAGE_PIN BN35 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[5]}] +set_property -dict {PACKAGE_PIN BM34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[5]}] +set_property -dict {PACKAGE_PIN BM44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[58]}] +set_property -dict {PACKAGE_PIN BN45 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[57]}] +set_property -dict {PACKAGE_PIN BP46 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[14]}] +set_property -dict {PACKAGE_PIN BN46 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[14]}] +set_property -dict {PACKAGE_PIN BM45 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[59]}] +set_property -dict {PACKAGE_PIN BN44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[56]}] +set_property -dict {PACKAGE_PIN BP44 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[61]}] +set_property -dict {PACKAGE_PIN BP43 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[60]}] +set_property -dict {PACKAGE_PIN BP47 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[63]}] +set_property -dict {PACKAGE_PIN BN47 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[62]}] +set_property -dict {PACKAGE_PIN BP42 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[15]}] +set_property -dict {PACKAGE_PIN BN42 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[15]}] +set_property -dict {PACKAGE_PIN BE50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[40]}] +set_property -dict {PACKAGE_PIN BE49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[41]}] +set_property -dict {PACKAGE_PIN BF48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[10]}] +set_property -dict {PACKAGE_PIN BF47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[10]}] +set_property -dict {PACKAGE_PIN BE51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[42]}] +set_property -dict {PACKAGE_PIN BD51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[43]}] +set_property -dict {PACKAGE_PIN BF50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[47]}] +set_property -dict {PACKAGE_PIN BG50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[46]}] +set_property -dict {PACKAGE_PIN BF52 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[44]}] +set_property -dict {PACKAGE_PIN BF51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[45]}] +set_property -dict {PACKAGE_PIN BG49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[11]}] +set_property -dict {PACKAGE_PIN BG48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[11]}] +set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[49]}] +set_property -dict {PACKAGE_PIN BH51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[50]}] +set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[12]}] +set_property -dict {PACKAGE_PIN BH47 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[12]}] +set_property -dict {PACKAGE_PIN BH50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[48]}] +set_property -dict {PACKAGE_PIN BH49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[51]}] +set_property -dict {PACKAGE_PIN BK50 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[52]}] +set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[55]}] +set_property -dict {PACKAGE_PIN BK51 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[53]}] +set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[54]}] +set_property -dict {PACKAGE_PIN BK49 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[13]}] +set_property -dict {PACKAGE_PIN BK48 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[13]}] +set_property -dict {PACKAGE_PIN BL30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[2]}] +set_property -dict {PACKAGE_PIN BM30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[3]}] +set_property -dict {PACKAGE_PIN BN30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[0]}] +set_property -dict {PACKAGE_PIN BN29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[0]}] +set_property -dict {PACKAGE_PIN BP32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[1]}] +set_property -dict {PACKAGE_PIN BN32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[0]}] +set_property -dict {PACKAGE_PIN BP31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[6]}] +set_property -dict {PACKAGE_PIN BN31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[7]}] +set_property -dict {PACKAGE_PIN BP29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[4]}] +set_property -dict {PACKAGE_PIN BP28 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[5]}] +set_property -dict {PACKAGE_PIN BM29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[1]}] +set_property -dict {PACKAGE_PIN BM28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[1]}] +set_property -dict {PACKAGE_PIN BH31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[9]}] +set_property -dict {PACKAGE_PIN BJ31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[8]}] +set_property -dict {PACKAGE_PIN BK30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[2]}] +set_property -dict {PACKAGE_PIN BJ29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[2]}] +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[10]}] +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[11]}] +set_property -dict {PACKAGE_PIN BH29 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[12]}] +set_property -dict {PACKAGE_PIN BH30 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[13]}] +set_property -dict {PACKAGE_PIN BF31 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[14]}] +set_property -dict {PACKAGE_PIN BG32 IOSTANDARD POD12_DCI} [get_ports {ddr_dq[15]}] +set_property -dict {PACKAGE_PIN BG30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_n[3]}] +set_property -dict {PACKAGE_PIN BG29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr_dqs_p[3]}] + +set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] +set_property PULLDOWN true [get_ports hbm_cattrip] + +set_false_path -from [get_pins chipset/chipset_impl/u280_polara_i/polara_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/*/C] -to [get_pins chipset/chipset_impl/init_calib_complete_f_reg/D] + +set_property USER_SLR_ASSIGNMENT SLR0 [get_cells [get_cells -of_objects [get_nets -of_objects [get_pins -hierarchical qdma_0/axi_aclk]]]] + + + diff --git a/piton/design/xilinx/alveou280/devices.xml b/piton/design/xilinx/alveou280/devices.xml new file mode 100644 index 000000000..8162e9c91 --- /dev/null +++ b/piton/design/xilinx/alveou280/devices.xml @@ -0,0 +1,57 @@ + + + + + chip + + + + mem + 0x0 + + 0x40000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + net + 0xfff0d00000 + 0x100000 + + diff --git a/piton/design/xilinx/alveou280/devices_ariane.xml b/piton/design/xilinx/alveou280/devices_ariane.xml new file mode 100644 index 000000000..67e4a6948 --- /dev/null +++ b/piton/design/xilinx/alveou280/devices_ariane.xml @@ -0,0 +1,56 @@ + + + + + chip + + + + mem + 0x80000000 + + 0x200000000 + + + iob + 0x9f00000000 + 0x10 + + + + uart + 0xfff0c2c000 + + 0xd4000 + + + + + + + + ariane_bootrom + 0xfff1010000 + 0x10000 + + + + diff --git a/piton/tools/bin/riscvlib.py b/piton/tools/bin/riscvlib.py index cc20337be..47b678a81 100644 --- a/piton/tools/bin/riscvlib.py +++ b/piton/tools/bin/riscvlib.py @@ -321,8 +321,8 @@ def main(): sysFreq = int(os.environ['CONFIG_SYS_FREQ']) timeStamp = time.strftime("%b %d %Y %H:%M:%S", time.localtime()) - gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) - get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/128, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) + gen_riscv_dts(devices, PITON_NUM_TILES, sysFreq, sysFreq/16384, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) + get_bootrom_info(devices, PITON_NUM_TILES, sysFreq, sysFreq/16384, sysFreq, os.environ['DV_ROOT']+"/design/chipset/rv64_platform/bootrom/", timeStamp) if __name__ == "__main__": main() diff --git a/piton/tools/bin/rv64_cc b/piton/tools/bin/rv64_cc index 2309139a3..160ad9419 100755 --- a/piton/tools/bin/rv64_cc +++ b/piton/tools/bin/rv64_cc @@ -33,14 +33,16 @@ RISCV_LDFLAGS="-static -nostartfiles -lm -Wl,--gc-sections -T ${DV_ROOT}/verif/d # Build #---------------------------------------------------------- RISCV_V_LLVM="${DV_ROOT}/design/chip/tile/ara/install/riscv-llvm/bin/clang" + RISCV_LINK_OPTS="-nostdlib ${RISCV_LDFLAGS} ${LLVM_FLAGS} ${LLVM_V_FLAGS} -DDEFINE_MALLOC -DDEFINE_REALLOC -DDEFINE_FREE -Werror-implicit-function-declaration -fno-math-errno -Wl,-Map=diag.map" RISCV_V_LLVM_OPTS="-DPREALLOCATE=1 -mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf $2 -DPITON_NUMTILES=${PITON_NUM_TILES}" + INCS="-I${DV_ROOT}/verif/diag/assembly/include/riscv/ariane" ARA_INCS="-I${DV_ROOT}/design/chip/tile/ara/apps/riscv-tests/isa/macros/vector" -${RISCV_V_LLVM} ${INCS} ${ARA_INCS} ${RISCV_V_LLVM_OPTS} -o diag.exe $1 \ +${RISCV_V_LLVM} ${INCS} ${ARA_INCS} ${RISCV_V_LLVM_OPTS} -o diag.exe $1 \ ${DV_ROOT}/verif/diag/assembly/include/riscv/ariane/syscalls.c \ ${DV_ROOT}/verif/diag/assembly/include/riscv/ariane/crt.S \ ${RISCV_LINK_OPTS} diff --git a/piton/tools/src/proto/alveou280/board.tcl b/piton/tools/src/proto/alveou280/board.tcl new file mode 100644 index 000000000..ca739787f --- /dev/null +++ b/piton/tools/src/proto/alveou280/board.tcl @@ -0,0 +1,45 @@ +# Copyright (c) 2016 Princeton University +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Princeton University nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# +# Board specific variables +# Not intended to be run standalone +# + +set BOARD_PART "" +set FPGA_PART "xcu280-fsvh2892-2l-e" +set VIVADO_FLOW_PERF_OPT 0 +set BOARD_DEFAULT_VERILOG_MACROS "ALVEO_BOARD" + + +# Create a block design containing PCIe and GPIO using the FPGA_PART variable +# It will produce the "polara_fpga.bd" file + +source $DV_ROOT/tools/src/proto/${BOARD}/polara_fpga.tcl + +# Grab the file from where the above tcl script has placed it +set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/alveou280/polara_fpga/polara_fpga] + + diff --git a/piton/tools/src/proto/alveou280/polara_fpga.tcl b/piton/tools/src/proto/alveou280/polara_fpga.tcl new file mode 100644 index 000000000..06b41694d --- /dev/null +++ b/piton/tools/src/proto/alveou280/polara_fpga.tcl @@ -0,0 +1,374 @@ + +################################################################ +# This is a generated script based on design: polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./tmp_proj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/alveou280/bd_alveo +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xcu280-fsvh2892-2L-e + set_property BOARD_PART xilinx.com:au280:part0:1.2 [current_project] +} + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/alveou280 +current_bd_design $design_name + + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create interface ports + set c0_ddr4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 ] + + set c0_ddr4_s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {300000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi + + set c0_ddr4_s_axi_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 c0_ddr4_s_axi_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $c0_ddr4_s_axi_ctrl + + set c0_sysclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 c0_sysclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $c0_sysclk + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + + # Create ports + set c0_ddr4_ui_clk [ create_bd_port -dir O -type clk c0_ddr4_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {c0_ddr4_s_axi:c0_ddr4_s_axi_ctrl} \ + ] $c0_ddr4_ui_clk + set c0_ddr4_ui_clk_sync_rst [ create_bd_port -dir O -type rst c0_ddr4_ui_clk_sync_rst ] + set c0_init_calib_complete [ create_bd_port -dir O c0_init_calib_complete ] + set chip_rstn [ create_bd_port -dir O -from 0 -to 0 chip_rstn ] + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set resetn [ create_bd_port -dir I -type rst resetn ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {2} \ + ] $axi_gpio_0 + + # Create instance: chip_rstn, and set properties + set chip_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 chip_rstn ] + set_property -dict [ list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DOUT_WIDTH {1} \ + ] $chip_rstn + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.CKE_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {1} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiNarrowBurst.VALUE_SRC {USER} \ + CONFIG.C0.DDR4_AxiIDWidth.VALUE_SRC {USER} \ + CONFIG.C0.DDR4_AxiIDWidth {7} \ + CONFIG.C0.DDR4_AxiNarrowBurst {true} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {15} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataMask {NONE} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_Specify_MandD {false} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.ODT_WIDTH {1} \ + ] $ddr4_0 + + # Create instance: proc_sys_rst_pcie, and set properties + set proc_sys_rst_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_rst_pcie ] + + # Create instance: qdma_0, and set properties + set qdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:qdma:4.0 qdma_0 ] + set_property -dict [ list \ + CONFIG.MAILBOX_ENABLE {true} \ + CONFIG.PF0_SRIOV_CAP_INITIAL_VF {4} \ + CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF1_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF1_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF2_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF2_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.PF3_MSIX_CAP_TABLE_SIZE_qdma {000} \ + CONFIG.PF3_SRIOV_CAP_INITIAL_VF {0} \ + CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {0} \ + CONFIG.SRIOV_CAP_ENABLE {true} \ + CONFIG.SRIOV_FIRST_VF_OFFSET {4} \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.barlite_mb_pf0 {1} \ + CONFIG.barlite_mb_pf1 {0} \ + CONFIG.barlite_mb_pf2 {0} \ + CONFIG.barlite_mb_pf3 {0} \ + CONFIG.coreclk_freq {250} \ + CONFIG.dma_intf_sel_qdma {AXI_MM} \ + CONFIG.en_axi_st_qdma {false} \ + CONFIG.flr_enable {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pcie_blk_locn {PCIE4C_X1Y0} \ + CONFIG.select_quad {GTY_Quad_227} \ + CONFIG.pf0_ari_enabled {true} \ + CONFIG.pf0_bar0_prefetchable_qdma {true} \ + CONFIG.pf0_bar2_prefetchable_qdma {true} \ + CONFIG.pf0_device_id {902F} \ + CONFIG.pf1_bar0_prefetchable_qdma {true} \ + CONFIG.pf1_bar2_prefetchable_qdma {true} \ + CONFIG.pf1_msix_enabled_qdma {false} \ + CONFIG.pf2_bar0_prefetchable_qdma {true} \ + CONFIG.pf2_bar2_prefetchable_qdma {true} \ + CONFIG.pf2_device_id {922F} \ + CONFIG.pf2_msix_enabled_qdma {false} \ + CONFIG.pf3_bar0_prefetchable_qdma {true} \ + CONFIG.pf3_bar2_prefetchable_qdma {true} \ + CONFIG.pf3_device_id {932F} \ + CONFIG.pf3_msix_enabled_qdma {false} \ + CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X16} \ + CONFIG.testname {mm} \ + ] $qdma_0 + + # Create instance: rst_ea_CLK0, and set properties + set rst_ea_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ea_CLK0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + ] $smartconnect_0 + + # Create instance: sys_rstn, and set properties + set sys_rstn [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sys_rstn ] + set_property -dict [ list \ + CONFIG.DIN_WIDTH {2} \ + ] $sys_rstn + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + ] $util_ds_buf + + # Create instance: vdd_0, and set properties + set vdd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vdd_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net C0_DDR4_S_AXI_CTRL_0_1 [get_bd_intf_ports c0_ddr4_s_axi_ctrl] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports c0_ddr4_s_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net c0_sysclk_1 [get_bd_intf_ports c0_sysclk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net qdma_0_M_AXI [get_bd_intf_pins qdma_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net qdma_0_M_AXI_LITE [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins qdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net qdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins qdma_0/pcie_mgt] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + + # Create port connections + connect_bd_net -net ARESETN_1 [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins rst_ea_CLK0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins chip_rstn/Din] [get_bd_pins sys_rstn/Din] + connect_bd_net -net chip_rstn_Dout [get_bd_ports chip_rstn] [get_bd_pins chip_rstn/Dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_ports c0_ddr4_ui_clk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins rst_ea_CLK0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_ports c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] + connect_bd_net -net ddr4_0_c0_init_calib_complete [get_bd_ports c0_init_calib_complete] [get_bd_pins ddr4_0/c0_init_calib_complete] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins qdma_0/soft_reset_n] [get_bd_pins qdma_0/sys_rst_n] + connect_bd_net -net qdma_0_axi_aclk [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins proc_sys_rst_pcie/slowest_sync_clk] [get_bd_pins qdma_0/axi_aclk] [get_bd_pins smartconnect_0/aclk1] + connect_bd_net -net qdma_0_axi_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_rst_pcie/ext_reset_in] [get_bd_pins qdma_0/axi_aresetn] + connect_bd_net -net qdma_0_phy_ready [get_bd_pins proc_sys_rst_pcie/dcm_locked] [get_bd_pins qdma_0/phy_ready] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins rst_ea_CLK0/ext_reset_in] + connect_bd_net -net rst_ea_CLK0_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ea_CLK0/peripheral_reset] + connect_bd_net -net sys_rstn_Dout [get_bd_pins rst_ea_CLK0/aux_reset_in] [get_bd_pins sys_rstn/Dout] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins qdma_0/sys_clk] [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins qdma_0/sys_clk_gt] [get_bd_pins util_ds_buf/IBUF_OUT] + connect_bd_net -net vdd_0_dout [get_bd_pins qdma_0/qsts_out_rdy] [get_bd_pins qdma_0/tm_dsc_sts_rdy] [get_bd_pins vdd_0/dout] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI_LITE] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces qdma_0/M_AXI] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces c0_ddr4_s_axi_ctrl] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + + + + # ########################################################### + # Final changes. Use this block to customize the bd + + # Decrease the PCIe speed for better timing results + + # ########################################################### + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} + + diff --git a/piton/tools/src/proto/block.list b/piton/tools/src/proto/block.list index 04a332390..01ef11a8f 100644 --- a/piton/tools/src/proto/block.list +++ b/piton/tools/src/proto/block.list @@ -25,11 +25,11 @@ # Format: # BlockID BlockPath Supported Board,Frequency(MHz),DDRSize(Mbytes) piton_aws ../../build/f1/piton_aws/design f1,62.5,4096 -system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768 -chipset chipset genesys2,66.667,1024;piton_board,50,0 +system . vc707,60,1024;genesys2,66.667,1024;nexysVideo,30,512;vcu118,100,2048;xupp3r,60,32768;alveou280,50,16384 +chipset chipset genesys2,8,1024;piton_board,50,0 passthru passthru piton_board,100,0 passthru_loopback fpga_tests/passthru_loopback piton_board,100,0 -chip chip genesys2,66.667,1024 +chip chip genesys2,66.667,1024;vc707,50,1024 chip_bridge_test_fpga fpga_tests/chip_bridge_test/chip_bridge_test_fpga genesys2,66.667,1024;piton_board,50,0 chip_bridge_test_chip fpga_tests/chip_bridge_test/chip_bridge_test_chip genesys2,66.667,1024;piton_board,50,0 memctrl_test fpga_tests/memio_unit_tests/memctrl_test genesys2,100,1024 diff --git a/piton/tools/src/proto/board.list b/piton/tools/src/proto/board.list index 6149781e9..d51b4ffed 100644 --- a/piton/tools/src/proto/board.list +++ b/piton/tools/src/proto/board.list @@ -30,3 +30,4 @@ nexysVideo vivado f1 vivado vcu118 vivado xupp3r vivado +alveou280 vivado diff --git a/piton/tools/src/proto/common/rtl_setup.tcl b/piton/tools/src/proto/common/rtl_setup.tcl index 7bcf1d82d..5e1ead991 100644 --- a/piton/tools/src/proto/common/rtl_setup.tcl +++ b/piton/tools/src/proto/common/rtl_setup.tcl @@ -28,7 +28,8 @@ # Not intended to be run standalone # -set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include" +set GLOBAL_INCLUDE_DIRS "${DV_ROOT}/design/include ${DV_ROOT}/design/chipset/include ${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/include ${DV_ROOT}/design/chip/tile/ariane/common/local/util ${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/include ${DV_ROOT}/design/chip/tile/ara/hardware/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src ${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/include ${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/include" + # RTL include files set GLOBAL_INCLUDE_FILES [list \ @@ -69,6 +70,8 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/common/rtl/bram_1rw_wrapper.v" \ "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ "${DV_ROOT}/design/common/rtl/synchronizer.v" \ + "${DV_ROOT}/design/common/rtl/noc_simple_splitter.v" \ + "${DV_ROOT}/design/common/rtl/noc_simple_merger.v" \ "${DV_ROOT}/design/chip/rtl/OCI.v" \ "${DV_ROOT}/design/chip/rtl/chip.v" \ "${DV_ROOT}/design/chip/pll/rtl/pll_top.v" \ @@ -394,155 +397,316 @@ set CHIP_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1d_tag.v" \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_data.v" \ "${DV_ROOT}/design/chip/tile/sparc/srams/rtl/sram_wrappers/sram_l1i_tag.v" \ + "${DV_ROOT}/design/chip/tile/pmesh_rvic_rtl/pmesh_rvic.sv" \ + "${DV_ROOT}/design/chip/tile/pmesh_rvic_rtl/rvic_wrap.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_config_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_soc_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi/src/axi_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_axi_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/wt_cache_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/include/axi_intf.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/polara_bootrom.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/riscv_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/ariane_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/acc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_soc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/ariane_axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/wt_cache_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/axi_intf.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/include/cvxif_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/cf_math_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/include/instr_tracer_pkg.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/include/cvxif_instr_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_master_connect.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_master_connect_rev.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_slave_connect.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/axi_slave_connect_rev.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/rrarbiter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/fifo_v1.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/deprecated/fifo_v2.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/fifo_v3.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/shift_reg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lfsr_8bit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lfsr.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/lzc.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/exp_backoff.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/rr_arb_tree.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/rstgen_bypass.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/cdc_2phase.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/unread.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/popcount.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/fpga/tc_clk_xilinx.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/fpga/tc_sram_xilinx.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/deprecated/cluster_clk_cells.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/local/util/tc_sram_xilinx_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/axi_adapter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ariane.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/controller.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/csr_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/csr_regfile.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ex_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/btb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/bht.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/ras.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_scan.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_queue.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/frontend/frontend.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/id_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/instr_realign.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/issue_read_operands.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/issue_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/load_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/load_store_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/lsu_bypass.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/mmu.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mult.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/multiplier.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/serdiv.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/perf_counters.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/ptw.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/ariane_regfile_ff.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/re_name.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/scoreboard.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/store_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/amo_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/store_unit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/tlb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/commit_stage.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_ctrl.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_missunit.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_wbuffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache_axi_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_l15_adapter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_cache_subsystem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/clint.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/axi_lite_interface.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/debug_rom/debug_rom.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_csrs.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_mem.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_top.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_cdc.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_sba.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/baremetal/bootrom.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/bootrom/linux/bootrom_linux.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_target.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/rv_plic_gateway.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_regmap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/rv_plic/rtl/plic_top.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf_pkg.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_cast_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_classifier.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_divsqrt_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_fma_multi.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_fma.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_noncomp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_block.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_fmt_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_opgroup_multifmt_slice.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_rounding.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/fpu/src/fpnew_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/acc_dispatcher.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/sram.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/fifo_v3.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/shift_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lfsr.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/lzc.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/exp_backoff.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/cdc_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/unread.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/popcount.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/tc_sram_fpga_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_clk_xilinx.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/axi_adapter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/alu.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/fpu_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/ariane.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cva6.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/branch_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/compressed_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/controller.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/csr_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/csr_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/ex_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/btb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/bht.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/ras.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_scan.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/instr_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/frontend/frontend.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/id_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/instr_realign.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/issue_read_operands.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/issue_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/load_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/load_store_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/lsu_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/mmu.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mult.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/multiplier.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/serdiv.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/perf_counters.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/ptw.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/ariane_regfile_ff.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/re_name.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/scoreboard.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/store_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/amo_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/store_unit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/mmu_sv39/tlb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/commit_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_ctrl.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_missunit.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_wbuffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_dcache.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/cva6_icache_axi_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_l15_adapter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/core/cache_subsystem/wt_cache_subsystem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/clint.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/clint/axi_lite_interface.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/debug_rom/debug_rom.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_csrs.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_top.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dm_sba.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/riscv_peripherals.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/openpiton/ariane_verilog_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/apb_to_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/register_interface/src/reg_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_fma.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/openhwgroup/cvfpu/src/fpnew_top.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp_entry.sv" \ \ + "${DV_ROOT}/design/chip/tile/ariane/core/pmp/src/pmp_entry.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/instr_tracer.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/common/local/util/instr_tracer_if.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/cvxif_example_coprocessor.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_example/instr_decoder.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/counter.sv" \ - "${DV_ROOT}/design/chip/tile/ariane/common/submodules/common_cells/src/delta_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/counter.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/src/delta_counter.sv" \ "${DV_ROOT}/design/chip/tile/ariane/core/cvxif_fu.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/reg_intf_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/top_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/tlul_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_reg_pkg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_regmap.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/plic_top.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/prim_subreg.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/prim_subreg_ext.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_gateway.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_reg_top.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/rv_plic_rtl/rtl/rv_plic_target.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/rvv_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/include/ara_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/sync_fifo.v " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axilite.sv " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/strb2mask.v" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/axilite_noc_bridge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/noc_response_axi.sv " \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/axi_noc_bridge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/openpiton/ara_verilog_wrap.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/accel_dispatcher_ideal.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_dispatcher.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_sequencer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_soc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ara_system.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_inval_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/axi_to_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/ctrl_registers.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/cva6_accel_first_pass_decoder.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/power_gating_generic.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/fixed_p_rounding.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queues_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/ara_popcnt.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_alu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/valu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vmfpu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/lane_sequencer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_div.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_fus_stage.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/lane.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/operand_requester.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/simd_mul.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/lane/vector_regfile.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/masku/masku.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/p2_stride_gen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu_op_dp.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/sldu/sldu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/addrgen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vldu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vlsu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/src/vlsu/vstu.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_detect.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/fifo_v3.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator_tx.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_omega_net.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/delta_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_to_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/clock_divider_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/fifo_v2.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/prioarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/pulp_sync.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_LFSR_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/rrarbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/clock_divider.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_fifo.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/fifo_v1.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/find_first_one.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/pulp_sync_wedge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/deprecated/generic_fifo_adv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/isochronous_spill_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sub_per_hash.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fifo.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/fall_through_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/exp_backoff.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rstgen.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_decode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lzc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_fifo_gray.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/id_queue.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cb_filter_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/serial_deglitch.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_arbiter_flushable.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/onehot_to_bin.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/clk_div.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fork.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_delay.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rr_arb_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/max_counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_arbiter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/addr_decode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/edge_propagator_rx.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/binary_to_gray.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/spill_register.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cb_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/spill_register_flushable.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/cdc_fifo_2phase.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/ecc_encode.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/plru_tree.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr_8bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/shift_reg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/lfsr_16bit.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_fork_dynamic.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/unread.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/popcount.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sync.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/rstgen_bypass.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/sync_wedge.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/gray_to_binary.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/mv_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/counter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/common_cells/src/stream_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_to_axi.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_src.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_modify_address.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_downsizer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_xbar.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_err_slv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_join.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_to_axi_lite.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_serializer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_converter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cut.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_dw_upsizer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_atop_filter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_burst_splitter.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_delayer.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_regs.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_to_apb.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_isolate.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_multicut.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_sim_mem.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_demux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_id_prepend.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mailbox.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_cdc_dst.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/axi/src/axi_lite_mux.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_intf.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_regs.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_err_slv.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_cdc.sv" \ + "${DV_ROOT}/design/chip/tile/ara/hardware/deps/apb/src/apb_demux.sv" \ + "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ ] + + set CHIP_INCLUDE_FILES [list \ ] @@ -611,6 +775,18 @@ set PASSTHRU_PRJ_IP_FILES [list \ ] set CHIPSET_RTL_IMPL_FILES [list \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/linux/bootrom_linux.sv" \ + "${DV_ROOT}/design/common/rtl/bram_1r1w_wrapper.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/gen2_polara_top.sv"\ + "${DV_ROOT}/design/chipset/rtl/polara_loopback_packet_gen.v" \ + "${DV_ROOT}/design/chipset/rtl/polara_debouncer.sv" \ + "${DV_ROOT}/design/chipset/rtl/polara_loopback.v" \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/baremetal/bootrom.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/axi_mem_if/src/axi2mem.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/axi/src/axi_pkg.sv" \ + "${DV_ROOT}/design/chip/tile/ariane/corev_apu/tb/axi_intf.sv" \ + "${DV_ROOT}/design/chipset/rv64_platform/bootrom/polara_bootrom.sv" \ + "${DV_ROOT}/design/common/rtl/noc_simple_merger.v" \ "${DV_ROOT}/design/common/rtl/bram_sdp_wrapper.v" \ "${DV_ROOT}/design/chipset/rtl/chipset.v" \ "${DV_ROOT}/design/chipset/rtl/chipset_impl.v" \ @@ -653,8 +829,10 @@ set CHIPSET_RTL_IMPL_FILES [list \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/uart_reseter.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/fake_boot_ctrl.v" \ "${DV_ROOT}/design/chipset/io_ctrl/rtl/eth_top.v" \ + "${DV_ROOT}/design/chipset/io_ctrl/rtl/int_pkt_gen.v" \ "${DV_ROOT}/design/chipset/mc/rtl/mc_top.v" \ "${DV_ROOT}/design/chipset/mc/rtl/f1_mc_top.v" \ + "${DV_ROOT}/design/chipset/mc/rtl/u280_polara_top.sv" \ "${DV_ROOT}/design/chipset/mc/rtl/noc_mig_bridge.v" \ "${DV_ROOT}/design/chipset/mc/rtl/memory_zeroer.v" \ "${DV_ROOT}/design/chipset/noc_axilite_bridge/rtl/noc_axilite_bridge.v" \ @@ -742,7 +920,7 @@ set CHIPSET_INCLUDE_FILES [list \ "${DV_ROOT}/design/chipset/include/uart16550_define.vh" \ "${DV_ROOT}/design/chipset/include/chipset_define.vh" \ "${DV_ROOT}/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_define.vh" \ - "${DV_ROOT}/design/chip/tile/ariane/src/common_cells/include/common_cells/registers.svh" + "${DV_ROOT}/design/chip/tile/ariane/vendor/pulp-platform/common_cells/include/common_cells/registers.svh" ] set CHIPSET_IP_FILE_PREFIXES [list \ diff --git a/piton/tools/src/proto/common/setup.tcl b/piton/tools/src/proto/common/setup.tcl index 3a2f15efa..c2de9f5b5 100644 --- a/piton/tools/src/proto/common/setup.tcl +++ b/piton/tools/src/proto/common/setup.tcl @@ -62,6 +62,20 @@ foreach ip_file ${ALL_IP_FILE_PREFIXES} { lappend ALL_XCO_IP_FILES "${ip_file}.xco" } +set ALL_BD_FILES [list ] +# Use block design only for alveou280 fpga emulation. +if { ${BOARD} == "alveou280" } { + foreach bd_file ${DESIGN_BD_FILES} { + lappend ALL_BD_FILES "${bd_file}.bd" + } +} +# Use block design if using --gen2chipset protosyn option +if { [ info exists ::env(POLARA_GEN2_CHIPSET) ] } { + foreach bd_file ${DESIGN_BD_FILES} { + lappend ALL_BD_FILES "${bd_file}.bd" + } +} + set ALL_COE_FILES [concat ${DESIGN_COE_IP_FILES}] set ALL_PRJ_IP_FILES [concat ${DESIGN_PRJ_IP_FILES}] @@ -94,7 +108,7 @@ if {[info exists ::env(PITON_PICO_HET)]} { } if {[info exists ::env(PITON_ARIANE)]} { - append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE" + append ALL_DEFAULT_VERILOG_MACROS " PITON_ARIANE PITON_RV64_PLATFORM PITON_RV64_DEBUGUNIT PITON_RV64_CLINT PITON_RV64_PLIC WT_DCACHE SYNTHESIS VLEN=4096 NR_LANES=4 ARIANE_ACCELERATOR_PORT L2_SEND_NC_REQ" } for {set k 0} {$k < $::env(PITON_NUM_TILES)} {incr k} { diff --git a/piton/tools/src/proto/fpga_lib.py b/piton/tools/src/proto/fpga_lib.py index 46f0870ea..a4f84c3eb 100644 --- a/piton/tools/src/proto/fpga_lib.py +++ b/piton/tools/src/proto/fpga_lib.py @@ -48,6 +48,7 @@ NOC_PAYLOAD_WIDTH = 512 STORAGE_BLOCK_BIT_WIDTH = { "ddr": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":128, "genesys2":256, @@ -56,6 +57,7 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -65,6 +67,7 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -76,6 +79,7 @@ STORAGE_ADDRESSABLE_BIT_WIDTH = { "ddr": { "vc707":64, "vcu118":64, + "alveou280":72, "xupp3r":64, "nexys4ddr":16, "genesys2":32, @@ -84,6 +88,7 @@ }, "bram": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, @@ -93,17 +98,21 @@ }, "dmw": { "vc707":512, "vcu118":512, + "alveou280":512, "xupp3r":512, "nexys4ddr":512, "genesys2":512, "nexysVideo":512, "piton_board":512, "f1":512 + }, + "hbm": { "alveou280":33 } } STORAGE_BIT_SIZE = { "ddr": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, @@ -112,6 +121,7 @@ }, "bram": { "vc707":16384*512, "vcu118":16384*512, + "alveou280":116384*512, "xupp3r":16384*512, "nexys4ddr":16384*512, "genesys2":16384*512, @@ -121,11 +131,14 @@ }, "dmw": { "vc707":8*2**30, "vcu118":2*8*2**30, + "alveou280":2*8*2**30, "xupp3r":32*8*2**30, "nexys4ddr":8*128*2**20, "genesys2":8*2**30, "nexysVideo":8*512*2**20, "f1":8*4*2**30 + }, + "hbm": { "alveou280":8*4*2*33 } } DW_BIT_SIZE = 64 @@ -183,9 +196,15 @@ def find_design_block(design_block): # Output: div - int - uart divider latch ############################################################################ def calcUARTLatch(design_data, board): + print("design_data[Boards]=", design_data["BOARDS"]) + print("design_data[Boards][board]=", design_data["BOARDS"][board]) + print("design_data[Boards][board][FREQ]=", design_data["BOARDS"][board]["FREQ"]) + print("Calculating (float(design_data[BOARDS][board][FREQ]) * 10**6) / (16 * UART_BAUD_RATE)") + div = (float(design_data["BOARDS"][board]["FREQ"]) * 10**6) / (16 * UART_BAUD_RATE); + print("Result float=", div) div = int(round(div)) - + print("Result int=", div) return div @@ -345,7 +364,7 @@ def buildProjectSuccess(log_dir): dbg.print_error("Check: %s" % fpath) return False - dbg.print_info("Project was build successfully!") + dbg.print_info("Project was built successfully!") return True diff --git a/piton/tools/src/proto/genesys2/board.tcl b/piton/tools/src/proto/genesys2/board.tcl index 7ccbede14..f20ebb585 100644 --- a/piton/tools/src/proto/genesys2/board.tcl +++ b/piton/tools/src/proto/genesys2/board.tcl @@ -28,7 +28,36 @@ # Not intended to be run standalone # -set BOARD_PART "" +set BOARD_PART "digilentinc.com:genesys2:part0:1.1" set FPGA_PART "xc7k325tffg900-2" set VIVADO_FLOW_PERF_OPT 0 set BOARD_DEFAULT_VERILOG_MACROS "GENESYS2_BOARD" + +# First check if we are doing loopback test +if { [ info exists ::env(POLARA_LOOPBACK) ] } { + # Create a block design containing a JTAG-AXI master using the FPGA_PART variable + # It will produce the "gen2_polara_fpga.bd" file + + source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga_loopback.tcl + + # Grab the file from where the above tcl script has placed it + set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga_loopback/gen2_polara_fpga_loopback] +} elseif { [ info exists ::env(POLARA_GEN2_CHIPSETSE) ] } { + # Single ended clock (for MIG input clock) has a specific block design + # Create a block design containing a JTAG-AXI master using the FPGA_PART variable + # It will produce the "gen2_polara_fpga.bd" file + + source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga_se_clk.tcl + + # Grab the file from where the above tcl script has placed it + set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga_se_clk/gen2_polara_fpga_se_clk] +} else { + # Create a block design containing a JTAG-AXI master using the FPGA_PART variable + # It will produce the "gen2_polara_fpga.bd" file + + source $DV_ROOT/tools/src/proto/${BOARD}/gen2_polara_fpga.tcl + + # Grab the file from where the above tcl script has placed it + set DESIGN_BD_FILES [list $DV_ROOT/design/chipset/xilinx/genesys2/gen2_polara_fpga/gen2_polara_fpga] + +} diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl new file mode 100644 index 000000000..7d9520c3b --- /dev/null +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga.tcl @@ -0,0 +1,217 @@ + +################################################################ +# This is a generated script based on design: gen2_polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source gen2_polara_fpga_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/genesys2/bd_gen2 +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xc7k325tffg900-2 +# create_project project_1 myproj -part xc7k325tffg900-2 + set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name gen2_polara_fpga + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/genesys2 +current_bd_design $design_name + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +################################################################## +# DESIGN PROCs +################################################################## + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr3_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ddr3_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {225022502} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $ddr3_axi + + set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] + + set mig_ddr3_sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mig_ddr3_sys_diff_clock ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $mig_ddr3_sys_diff_clock + + + # Create ports + set mig_ddr3_init_calib_complete [ create_bd_port -dir O mig_ddr3_init_calib_complete ] + set mig_ddr3_sys_rst_n [ create_bd_port -dir I -type rst mig_ddr3_sys_rst_n ] + set mig_ddr3_ui_clk [ create_bd_port -dir O -type clk mig_ddr3_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {ddr3_axi} \ + CONFIG.FREQ_HZ {225022502} \ + ] $mig_ddr3_ui_clk + set mig_ddr3_ui_clk_sync_rst [ create_bd_port -dir O -type rst mig_ddr3_ui_clk_sync_rst ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $mig_ddr3_ui_clk_sync_rst + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + set_property -dict [ list \ + CONFIG.M_AXI_DATA_WIDTH {32} \ + ] $jtag_axi_0 + + # Create instance: mig_7series_0, and set properties + set mig_7series_0_gen2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0_gen2 ] + set_property -dict [ list \ + CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \ + ] $mig_7series_0_gen2 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $smartconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net mig_7series_0_gen2_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0_gen2/DDR3] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0_gen2/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net sys_diff_clock_1 [get_bd_intf_ports mig_ddr3_sys_diff_clock] [get_bd_intf_pins mig_7series_0_gen2/SYS_CLK] + + # Create port connections + connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0_gen2/init_calib_complete] + connect_bd_net -net mig_7series_0_ui_clk [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0_gen2/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0_gen2/ui_clk_sync_rst] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0_gen2/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0_gen2/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] + + # Create address segments + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0_gen2/memmap/memaddr] -force + assign_bd_address -offset 0x80000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0_gen2/memmap/memaddr] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +close_project + +file delete -force ${tmp_build_dir}/${tmp_prj} diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl new file mode 100644 index 000000000..cb283f084 --- /dev/null +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_loopback.tcl @@ -0,0 +1,173 @@ + +################################################################ +# This is a generated script based on design: gen2_polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source gen2_polara_fpga_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/genesys2/bd_gen2 +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xc7k325tffg900-2 + # create_project project_1 myproj -part xc7k325tffg900-2 + set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name gen2_polara_fpga_loopback + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/genesys2 +current_bd_design $design_name + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set polara_gen2chipset_bus_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_i ] + + set polara_gen2chipset_bus_o [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_o ] + + + # Create ports + set bd_clk [ create_bd_port -dir I -type clk -freq_hz 40000000 bd_clk ] + set mig_ddr3_sys_rst_n [ create_bd_port -dir I -type rst mig_ddr3_sys_rst_n ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO2_WIDTH {2} \ + CONFIG.C_GPIO_WIDTH {12} \ + CONFIG.C_IS_DUAL {1} \ + CONFIG.C_TRI_DEFAULT {0x00000300} \ + ] $axi_gpio_0 + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + set_property -dict [ list \ + CONFIG.M_AXI_DATA_WIDTH {32} \ + ] $jtag_axi_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus_o] [get_bd_intf_pins axi_gpio_0/GPIO] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports polara_gen2chipset_bus_i] [get_bd_intf_pins axi_gpio_0/GPIO2] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + + # Create port connections + connect_bd_net -net aclk_0_1 [get_bd_ports bd_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins proc_sys_reset_0/ext_reset_in] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl new file mode 100644 index 000000000..dfc112c05 --- /dev/null +++ b/piton/tools/src/proto/genesys2/gen2_polara_fpga_se_clk.tcl @@ -0,0 +1,417 @@ + +################################################################ +# This is a generated script based on design: gen2_polara_fpga +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source gen2_polara_fpga_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set DV_ROOT $::env(DV_ROOT) +set PITON_ROOT $::env(PITON_ROOT) + +set tmp_build_dir ${PITON_ROOT}/build/genesys2/bd_gen2 +set tmp_prj "create_bd" + +file delete -force ${tmp_build_dir}/${tmp_prj} + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project -force ${tmp_build_dir}/${tmp_prj} -part xc7k325tffg900-2 +# create_project project_1 myproj -part xc7k325tffg900-2 + set_property BOARD_PART digilentinc.com:genesys2:part0:1.1 [current_project] +} + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name gen2_polara_fpga_se_clk + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name -dir $DV_ROOT/design/chipset/xilinx/genesys2 +current_bd_design $design_name + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +################################################################## +# MIG PRJ FILE TCL PROCs +################################################################## + +proc write_mig_file_gen2_polara_fpga_se_clk_mig_7series_0_0 { str_mig_prj_filepath } { + + file mkdir [ file dirname "$str_mig_prj_filepath" ] + set mig_prj_file [open $str_mig_prj_filepath w+] + + puts $mig_prj_file {} + puts $mig_prj_file {} + puts $mig_prj_file { } + puts $mig_prj_file {} + puts $mig_prj_file { gen2_polara_fpga_mig_7series_0_0} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { OFF} + puts $mig_prj_file { 1024} + puts $mig_prj_file { ON} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { xc7k325t-ffg900/-2} + puts $mig_prj_file { 4.2} + puts $mig_prj_file { No Buffer} + puts $mig_prj_file { Use System Clock} + puts $mig_prj_file { ACTIVE LOW} + puts $mig_prj_file { FALSE} + puts $mig_prj_file { 0} + puts $mig_prj_file { 50 Ohms} + puts $mig_prj_file { 0} + puts $mig_prj_file { } + puts $mig_prj_file { DDR3_SDRAM/Components/MT41J256m16XX-107} + puts $mig_prj_file { 1250} + puts $mig_prj_file { 2.0V} + puts $mig_prj_file { 4:1} + puts $mig_prj_file { 200} + puts $mig_prj_file { 0} + puts $mig_prj_file { 800} + puts $mig_prj_file { 1.000} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { 32} + puts $mig_prj_file { 1} + puts $mig_prj_file { 1} + puts $mig_prj_file { Disabled} + puts $mig_prj_file { Normal} + puts $mig_prj_file { 4} + puts $mig_prj_file { FALSE} + puts $mig_prj_file { } + puts $mig_prj_file { 15} + puts $mig_prj_file { 10} + puts $mig_prj_file { 3} + puts $mig_prj_file { 1.5V} + puts $mig_prj_file { 1073741824} + puts $mig_prj_file { BANK_ROW_COLUMN} + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file { 8 - Fixed} + puts $mig_prj_file { Sequential} + puts $mig_prj_file { 11} + puts $mig_prj_file { Normal} + puts $mig_prj_file { No} + puts $mig_prj_file { Slow Exit} + puts $mig_prj_file { Enable} + puts $mig_prj_file { RZQ/7} + puts $mig_prj_file { Disable} + puts $mig_prj_file { Enable} + puts $mig_prj_file { RZQ/6} + puts $mig_prj_file { 0} + puts $mig_prj_file { Disabled} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { Output Buffer Enabled} + puts $mig_prj_file { Full Array} + puts $mig_prj_file { 8} + puts $mig_prj_file { Enabled} + puts $mig_prj_file { Normal} + puts $mig_prj_file { Dynamic ODT off} + puts $mig_prj_file { AXI} + puts $mig_prj_file { } + puts $mig_prj_file { RD_PRI_REG} + puts $mig_prj_file { 30} + puts $mig_prj_file { 256} + puts $mig_prj_file { 3} + puts $mig_prj_file { 0} + puts $mig_prj_file { } + puts $mig_prj_file { } + puts $mig_prj_file {} + + close $mig_prj_file +} +# End of write_mig_file_gen2_polara_fpga_se_clk_mig_7series_0_0() + + + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr3_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ddr3_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {200000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $ddr3_axi + + set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ] + + set polara_gen2chipset_bus_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_i ] + + set polara_gen2chipset_bus_o [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 polara_gen2chipset_bus_o ] + + + # Create ports + set mig_ddr3_init_calib_complete [ create_bd_port -dir O mig_ddr3_init_calib_complete ] + set mig_ddr3_sys_rst_n [ create_bd_port -dir I -type rst mig_ddr3_sys_rst_n ] + set mig_ddr3_sys_se_clock_clk [ create_bd_port -dir I -type clk mig_ddr3_sys_se_clock_clk ] + set mig_ddr3_ui_clk [ create_bd_port -dir O -type clk mig_ddr3_ui_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {ddr3_axi} \ + CONFIG.FREQ_HZ {200000000} \ + ] $mig_ddr3_ui_clk + set mig_ddr3_ui_clk_sync_rst [ create_bd_port -dir O -type rst mig_ddr3_ui_clk_sync_rst ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $mig_ddr3_ui_clk_sync_rst + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO2_WIDTH {2} \ + CONFIG.C_GPIO_WIDTH {12} \ + CONFIG.C_IS_DUAL {1} \ + CONFIG.C_TRI_DEFAULT {0x00000300} \ + ] $axi_gpio_0 + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + set_property -dict [ list \ + CONFIG.M_AXI_DATA_WIDTH {32} \ + ] $jtag_axi_0 + + # Create instance: mig_7series_0, and set properties + set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.2 mig_7series_0 ] + + # Generate the PRJ File for MIG + set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ] + set str_mig_file_name mig_b.prj + set str_mig_file_path ${str_mig_folder}/${str_mig_file_name} + + write_mig_file_gen2_polara_fpga_se_clk_mig_7series_0_0 $str_mig_file_path + + set_property -dict [ list \ + CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \ + CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.XML_INPUT_FILE {mig_b.prj} \ + ] $mig_7series_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {2} \ + ] $smartconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net S01_AXI_0_1 [get_bd_intf_ports ddr3_axi] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports polara_gen2chipset_bus_o] [get_bd_intf_pins axi_gpio_0/GPIO] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports polara_gen2chipset_bus_i] [get_bd_intf_pins axi_gpio_0/GPIO2] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig_7series_0/DDR3] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins mig_7series_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] + + # Create port connections + connect_bd_net -net mig_7series_0_init_calib_complete [get_bd_ports mig_ddr3_init_calib_complete] [get_bd_pins mig_7series_0/init_calib_complete] + connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_ports mig_ddr3_ui_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_ports mig_ddr3_ui_clk_sync_rst] [get_bd_pins mig_7series_0/ui_clk_sync_rst] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins mig_7series_0/aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net sys_clk_i_0_1 [get_bd_ports mig_ddr3_sys_se_clock_clk] [get_bd_pins mig_7series_0/sys_clk_i] + connect_bd_net -net sys_rst_0_1 [get_bd_ports mig_ddr3_sys_rst_n] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] + + # Create address segments + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces ddr3_axi] [get_bd_addr_segs mig_7series_0/memmap/memaddr] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl new file mode 100644 index 000000000..333a9b7ec --- /dev/null +++ b/piton/tools/src/proto/genesys2/jtag_axi_commands.tcl @@ -0,0 +1,281 @@ +# #################################################################### +# +# test_jtag_axi.tcl +# +# Author : Raphael Rowley (2024/07) +# +# Description : +# Useful commands for JTAG-AXI Xilinx IP on Genesys Chipset +# +# #################################################################### + +# Inspired by: https://www.xilinx.com/video/software/jtag-to-axi-master-core.html +# AXI GPIO documentation: https://docs.amd.com/v/u/en-US/pg144-axi-gpio + +# Assumptions: +# core is named hw_axi_1 +# DDR3 base address 0x0000_0000 +# GPIO base address 0x4000_0000 + +# Channel 1 GPIO mapping (outputs) +# Channel 1 AXI GPIO Data Register Address Space Offset: 0x0000 +# 0 (LSB): chip_rst_n +# 1: chip_async_mux +# 2: chip_clk_en +# 3: chip_clk_mux_sel +# 4: fll_rst_n +# 5: fll_bypass +# 6: fll_opmode +# 7: fll_cfg_req +# 11-8: fll_range[3:0] + +# Channel 2 GPIO mapping (inputs) +# Channel 2 AXI GPIO Data Register Address Space Offset: 0x0008 +# 0: fll_lock +# 1: fll_clkdiv +# set_msg_config -id "Labtoolstcl 44-481" -limit 5500 + +# #################################################################### +# Init +# #################################################################### +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] + +# #################################################################### +# Loopback flow. We are not using FLL +# #################################################################### +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_async_mux = 1, chip_clk_en = 1, chip_clk_mux_sel = 1, rst on +create_hw_axi_txn -force cfgrst [get_hw_axis hw_axi_1] -address 40000000 -data {0000000E} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrst] +# 4. cfg take off rst +create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {0000000F} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrstoff] + +# #################################################################### +# Loopback flow. We are not using FLL. All synchronous +# #################################################################### +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_async_mux = 0, chip_clk_en = 1, chip_clk_mux_sel = 1, rst on +create_hw_axi_txn -force cfgrst [get_hw_axis hw_axi_1] -address 40000000 -data {0000000C} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrst] +# 4. cfg take off rst +create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {0000000D} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrstoff] + +# #################################################################### +# Loopback flow. FLL +# #################################################################### +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# f_fll = 2^2 * f_ref +# ------------------------------------------ +# 3. Set opmode = 1, fll_rst_n = 1, fll_range = 0010 +create_hw_axi_txn -force op2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000250} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2rstoff] +# 4. Set cfgreq = 1 +create_hw_axi_txn -force op2cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000002D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2cfg] +# 5. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op2rstoff] +# FLL previously configured with range = 2 +# 7. Keep the config but activate: async_mux = 1, clk_en = 1 +create_hw_axi_txn -force en2rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000256} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rston] +# 8. Release the reset +create_hw_axi_txn -force en2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000257} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rstoff] + + +# #################################################################### +# Genesys 2 Memory Test +# #################################################################### +# 2. Create a write transaction (16 word AXI burst write) +create_hw_axi_txn -force write0 [get_hw_axis hw_axi_1] -address 00000000 -data {FFFFFFFF_EEEEEEEE_DDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA_99999999_88888888_77777777_66666666_55555555_44444444_33333333_22222222_11111111_00000000} -len 16 -type write + +# 3. Run the write transaction +run_hw_axi [get_hw_axi_txns write0] + +# 4. Create a read transaction (16 word AXI burst read) +create_hw_axi_txn -force read0 [get_hw_axis hw_axi_1] -address 00000000 -len 16 -type read + +# 5. Run the read transaction +run_hw_axi [get_hw_axi_txns read0] + +# #################################################################### +# VC707 chip emulation useful commands +# #################################################################### +# 6. Assert chip reset_n +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] + +# 7. Deassert chip reset_n +create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rstoff] + +# #################################################################### +# Polara ASIC useful commands +# #################################################################### + +# ------------------------------------------ +# FLL Tests (chip stays in reset) +# ------------------------------------------ +# Test bypass +# ------------------------------------------ +create_hw_axi_txn -force fllrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000010} -len 1 -type write +run_hw_axi [get_hw_axi_txns fllrstoff] +# 1. Set bypass = 1, opmode = 1, fll_rst_n = 1 +create_hw_axi_txn -force bypassrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000070} -len 1 -type write +run_hw_axi [get_hw_axi_txns bypassrstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force bypasscfg [get_hw_axis hw_axi_1] -address 40000000 -data {000000F0} -len 1 -type write +run_hw_axi [get_hw_axi_txns bypasscfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns bypassrstoff] +# 4. Reset everything +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^0 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0000 +create_hw_axi_txn -force oprstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000050} -len 1 -type write +run_hw_axi [get_hw_axi_txns oprstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force opcfg [get_hw_axis hw_axi_1] -address 40000000 -data {000000D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns opcfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns oprstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^1 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0001 +create_hw_axi_txn -force op1rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000150} -len 1 -type write +run_hw_axi [get_hw_axi_txns op1rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op1cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000001D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op1cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op1rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^2 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0010 +create_hw_axi_txn -force op2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000250} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op2cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000002D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op2cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op2rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^4 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 0100 +create_hw_axi_txn -force op4rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000350} -len 1 -type write +run_hw_axi [get_hw_axi_txns op4rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op4cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000003D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op4cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op4rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] +# ------------------------------------------ +# Test FLL, f_fll = 2^8 * f_ref +# ------------------------------------------ +# 1. Set opmode = 1, fll_rst_n = 1, fll_range = 1000 +create_hw_axi_txn -force op8rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000850} -len 1 -type write +run_hw_axi [get_hw_axi_txns op8rstoff] +# 2. Set cfgreq = 1 +create_hw_axi_txn -force op8cfg [get_hw_axis hw_axi_1] -address 40000000 -data {000008D0} -len 1 -type write +run_hw_axi [get_hw_axi_txns op8cfg] +# 3. Set cfgreq = 0 +run_hw_axi [get_hw_axi_txns op8rstoff] +# 4. Reset everything +run_hw_axi [get_hw_axi_txns rston] + +# ------------------------------------------ +# Hello world, no FLL (brouillon) +# ------------------------------------------ +# 1. rst_n off +create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rstoff] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_async_mux = 1, chip_clk_en = 1, chip_clk_mux_sel = 1, rst on +create_hw_axi_txn -force cfgrst [get_hw_axis hw_axi_1] -address 40000000 -data {0000000E} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrst] +# 4. cfg take off rst +create_hw_axi_txn -force cfgrstoff [get_hw_axis hw_axi_1] -address 40000000 -data {0000000F} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns cfgrstoff] + + +# ------------------------------------------ +# Hello world, with FLL +# ------------------------------------------ +# FLL previously configured with range = 2 +# 1. Keep the config but activate: async_mux = 1, clk_en = 1 +create_hw_axi_txn -force en2rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000256} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rston] +# 2. Release the reset +create_hw_axi_txn -force en2rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000257} -len 1 -type write +run_hw_axi [get_hw_axi_txns en2rstoff] + +# Does not seem to work + +# ------------------------------------------ +# Hello world, with FLL +# ------------------------------------------ +# 1. rst_n off +create_hw_axi_txn -force rstoff [get_hw_axis hw_axi_1] -address 40000000 -data {00000001} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rstoff] +# 2. rst_n on +create_hw_axi_txn -force rston [get_hw_axis hw_axi_1] -address 40000000 -data {00000000} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns rston] +# 3. chip_clk_mux_sel = 1 (seems to work cuz current goes up) +create_hw_axi_txn -force muxon [get_hw_axis hw_axi_1] -address 40000000 -data {00000008} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns muxon] +# 3. chip_clk_en = 1 +create_hw_axi_txn -force enon [get_hw_axis hw_axi_1] -address 40000000 -data {0000000C} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns enon] +# 4. Take rst off (current goes down a bit) +create_hw_axi_txn -force syson [get_hw_axis hw_axi_1] -address 40000000 -data {0000000D} -len 1 -type write +# Run it +run_hw_axi [get_hw_axi_txns syson] diff --git a/piton/tools/src/proto/genesys2/test_jtag_axi.tcl b/piton/tools/src/proto/genesys2/test_jtag_axi.tcl new file mode 100644 index 000000000..fd393d734 --- /dev/null +++ b/piton/tools/src/proto/genesys2/test_jtag_axi.tcl @@ -0,0 +1,31 @@ +# #################################################################### +# +# test_jtag_axi.tcl +# +# Author : Raphael Rowley (2024/06) +# +# Description : +# Script to automate testing of JTAG-AXI Xilinx IP on Genesys Chipset +# +# #################################################################### + +# Inspired by: https://www.xilinx.com/video/software/jtag-to-axi-master-core.html + +# Assumptions: +# core is named hw_axi_1 +# DDR3 base address 0x0000_0000 + +# 1. Reset the core +reset_hw_axi [get_hw_axis hw_axi_1] + +# 2. Create a write transaction (16 word AXI burst write) +create_hw_axi_txn -force write0 [get_hw_axis hw_axi_1] -address 00000000 -data {FFFFFFFF_EEEEEEEE_DDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA_99999999_88888888_77777777_66666666_55555555_44444444_33333333_22222222_11111111_00000000} -len 16 -type write + +# 3. Run the write transaction +run_hw_axi [get_hw_axi_txns write0] + +# 4. Create a read transaction (16 word AXI burst read) +create_hw_axi_txn -force read0 [get_hw_axis hw_axi_1] -address 00000000 -len 16 -type read + +# 5. Run the read transaction +run_hw_axi [get_hw_axi_txns read0] diff --git a/piton/tools/src/proto/ila_analyze.py b/piton/tools/src/proto/ila_analyze.py new file mode 100644 index 000000000..4fc6615eb --- /dev/null +++ b/piton/tools/src/proto/ila_analyze.py @@ -0,0 +1,238 @@ +#!/usr/bin/env python3 +# +# +##################################################################### +# Filename : ila_analze.py +# Version : +# Created On : 2024-08-07 +# Author : Raphael Rowley +# Company : Polytechnique Montreal +# Email : raphael.rowley@polymtl.ca +# +# Description : Analyzes data got from Polara testing with ILA +# +##################################################################### + +import argparse +import csv + +INTERVAL_SAMPLES = 25 +RADIX = 'Radix - UNSIGNED' +HEADERS = ['Sample in Buffer', 'Sample in Window', 'TRIGGER', 'fpga_bridge/fpga_chip_out/serial_buffer_channel[1:0]', 'fpga_bridge/fpga_chip_out/credit_from_chip_ff[2:0]', 'fpga_bridge/fpga_chip_out/separator/D[31:0]', 'u_ila_0_data_channel_fff[1:0]', 'fpga_bridge/fpga_chip_in/credit_fifo_out[2:0]', 'u_ila_0_buffered_data[63:0]', 'u_ila_0_buffered_channel[1:0]'] + +ser_buff_channff0 = '0' +cred_frm_chip0 = '0' +d0 = '00000000' +channfff0 = '2' +credfifo_out0 = '0' +buff_data0 = '8083800800000000' +buff_chan0 = '0' + +ser_buff_channff1 = '0' +cred_frm_chip1 = '0' +d1 = '00000000' +channfff1 = '2' +credfifo_out1 = '0' +buff_data1 = '8000000080838008' +buff_chan1 = '2' + +ser_buff_channff2 = '0' +cred_frm_chip2 = '0' +d2 = '00000000' +channfff2 = '2' +credfifo_out2 = '0' +buff_data2 = '00000b0080838008' +buff_chan2 = '0' + +ser_buff_channff3 = '0' +cred_frm_chip3 = '0' +d3 = '00000000' +channfff3 = '2' +credfifo_out3 = '0' +buff_data3 = '00fff10100000b00' +buff_chan3 = '2' + +ser_buff_channff4 = '0' +cred_frm_chip4 = '0' +d4 = '00000000' +channfff4 = '2' +credfifo_out4 = '0' +buff_data4 = '0000000000000b00' +buff_chan4 = '0' + +def packet_compare(packet, ser_buff_channff, cred_frm_chip, d, channfff, credfifo_out, buff_data, buff_chan): + if packet == 0: + if ser_buff_channff == ser_buff_channff0: + if cred_frm_chip == cred_frm_chip0: + if d == d0: + if channfff == channfff0: + if credfifo_out == credfifo_out0: + if buff_data == buff_data0: + if buff_chan == buff_chan0: + return 0 + else: + print("In packet 0, buff_chan is", buff_chan, "not", buff_chan0) + else: + print("In packet 0, buff_data is", buff_data, "not", buff_data0) + else: + print("In packet 0, credfifo_out is", credfifo_out, "not", credfifo_out0) + else: + print("In packet 0, channfff is", channfff, "not", channfff0) + else: + print("In packet 0, d is", d, "not", d0) + else: + print("In packet 0, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip0) + else: + print("In packet 0, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff0) + if packet == 1: + if ser_buff_channff == ser_buff_channff1: + if cred_frm_chip == cred_frm_chip1: + if d == d1: + if channfff == channfff1: + if credfifo_out == credfifo_out1: + if buff_data == buff_data1: + if buff_chan == buff_chan1: + return 0 + else: + print("In packet 1, buff_chan is", buff_chan, "not", buff_chan1) + else: + print("In packet 1, buff_data is", buff_data, "not", buff_data1) + else: + print("In packet 1, credfifo_out is", credfifo_out, "not", credfifo_out1) + else: + print("In packet 1, channfff is", channfff, "not", channfff1) + else: + print("In packet 1, d is", d, "not", d1) + else: + print("In packet 1, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip1) + else: + print("In packet 1, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff1) + if packet == 2: + if ser_buff_channff == ser_buff_channff2: + if cred_frm_chip == cred_frm_chip2: + if d == d2: + if channfff == channfff2: + if credfifo_out == credfifo_out2: + if buff_data == buff_data2: + if buff_chan == buff_chan2: + return 0 + else: + print("In packet 2, buff_chan is", buff_chan, "not", buff_chan2) + else: + print("In packet 2, buff_data is", buff_data, "not", buff_data2) + else: + print("In packet 2, credfifo_out is", credfifo_out, "not", credfifo_out2) + else: + print("In packet 2, channfff is", channfff, "not", channfff2) + else: + print("In packet 2, d is", d, "not", d2) + else: + print("In packet 2, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip2) + else: + print("In packet 2, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff2) + if packet == 3: + if ser_buff_channff == ser_buff_channff3: + if cred_frm_chip == cred_frm_chip3: + if d == d3: + if channfff == channfff3: + if credfifo_out == credfifo_out3: + if buff_data == buff_data3: + if buff_chan == buff_chan3: + return 0 + else: + print("In packet 3, buff_chan is", buff_chan, "not", buff_chan3) + else: + print("In packet 3, buff_data is", buff_data, "not", buff_data3) + else: + print("In packet 3, credfifo_out is", credfifo_out, "not", credfifo_out3) + else: + print("In packet 3, channfff is", channfff, "not", channfff3) + else: + print("In packet 3, d is", d, "not", d3) + else: + print("In packet 3, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip3) + else: + print("In packet 3, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff3) + if packet == 4: + if ser_buff_channff == ser_buff_channff4: + if cred_frm_chip == cred_frm_chip4: + if d == d4: + if channfff == channfff4: + if credfifo_out == credfifo_out4: + if buff_data == buff_data4: + if buff_chan == buff_chan4: + return 0 + else: + print("In packet 4, buff_chan is", buff_chan, "not", buff_chan4) + else: + print("In packet 4, buff_data is", buff_data, "not", buff_data4) + else: + print("In packet 4, credfifo_out is", credfifo_out, "not", credfifo_out4) + else: + print("In packet 4, channfff is", channfff, "not", channfff4) + else: + print("In packet 4, d is", d, "not", d4) + else: + print("In packet 4, cred_frm_chip is", cred_frm_chip, "not", cred_frm_chip4) + else: + print("In packet 4, ser_buff_channff is", ser_buff_channff, "not", ser_buff_channff4) + +def main(): + + # Init + parser = argparse.ArgumentParser(description='Process ILA saved data.') + parser.add_argument('-f', '--file', help='File to analyze (assumes CSV).') + args = parser.parse_args() + + # Check inputs + if len(args.file) < 1: + print("Empty file provided") + return -1 + datafile = args.file + + # Load CSV + with open(datafile, newline='') as datacsv: + trigreader = csv.DictReader(datacsv) + + # Find trigger + for row in trigreader: + if row['TRIGGER'] == '1': + trigpoint = row['Sample in Buffer'] + print("Found trigger point, it is: ", trigpoint) + break + iterator = 0 + iterator1 = 0 + iterator2 = 0 + iterator3 = 0 + iterator4 = 0 + datacsv.seek(0) + datareader = csv.DictReader(datacsv) + print(datareader.fieldnames) + # Analyze data + for row in datareader: + if row['Sample in Buffer'] != RADIX: + if (int(row['Sample in Buffer']) >= int(trigpoint)) and (int(row['Sample in Buffer']) < int(trigpoint) + INTERVAL_SAMPLES): + #print("First packet", iterator, "Sample:", row['Sample in Buffer']) + packet_compare(0, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (2*INTERVAL_SAMPLES)): + #print("Second packet", iterator1, "Sample:", row['Sample in Buffer']) + packet_compare(1, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator1 += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (2*INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (3*INTERVAL_SAMPLES)): + #print("Third packet", iterator2, "Sample:", row['Sample in Buffer']) + packet_compare(2, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator2 += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (3*INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (4*INTERVAL_SAMPLES)): + #print("Fourth packet", iterator3, "Sample:", row['Sample in Buffer']) + packet_compare(3, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator3 += 1 + elif (int(row['Sample in Buffer']) >= int(trigpoint) + (4*INTERVAL_SAMPLES)) and (int(row['Sample in Buffer']) < int(trigpoint) + (5*INTERVAL_SAMPLES)): + #print("Fifth packet", iterator4, "Sample:", row['Sample in Buffer']) + packet_compare(4, row[HEADERS[3]], row[HEADERS[4]], row[HEADERS[5]], row[HEADERS[6]], row[HEADERS[7]], row[HEADERS[8]], row[HEADERS[9]]) + iterator4 += 1 + +if __name__ == '__main__': + + main() + diff --git a/piton/tools/src/proto/pitonstream,1.0 b/piton/tools/src/proto/pitonstream,1.0 index 18db5b434..f3d38d2be 100755 --- a/piton/tools/src/proto/pitonstream,1.0 +++ b/piton/tools/src/proto/pitonstream,1.0 @@ -172,7 +172,8 @@ def configureUART(port): stopbits=serial.STOPBITS_ONE, timeout=0 ) - except: + except Exception as error: + print("An exception occurred:", error) print_error("Can not open serial device %s" % port_full) print_error("Provide correct device name using -p option") return None @@ -362,6 +363,7 @@ def main(): st_brd = StorageBoard("bram", options.board) if options.storage == "ddr": + print("Storage option selected is ddr.") st_brd = StorageBoard("dmw", options.board) # Get list of tests and board configuration diff --git a/piton/tools/src/proto/protosyn,2.5 b/piton/tools/src/proto/protosyn,2.5 index 376e7143f..06716e125 100755 --- a/piton/tools/src/proto/protosyn,2.5 +++ b/piton/tools/src/proto/protosyn,2.5 @@ -64,6 +64,7 @@ def usage(): print(" genesys2", file=sys.stderr) print(" nexysVideo", file=sys.stderr) print(" f1", file=sys.stderr) + print(" alveou280", file=sys.stderr) print("\n -d, --design ", file=sys.stderr) print(" Name of design module to synthesize. The default is 'system', which", file=sys.stderr) print(" synthesizes a full system with chip and chipset. See", file=sys.stderr) @@ -74,6 +75,7 @@ def usage(): print(" pico (32bit RISCV core)", file=sys.stderr) print(" pico_het (heterogeneous pico+sparc arrangement)", file=sys.stderr) print(" ariane (64bit RISCV core)", file=sys.stderr) + print(" ara (64bit RISCV vec core)", file=sys.stderr) print("\n --network_config ", file=sys.stderr) print(" Name of the network type to be used:", file=sys.stderr) print(" 2dmesh_config (default)", file=sys.stderr) @@ -141,6 +143,23 @@ def usage(): print(" Number of jobs to use in Vivado implementation flow", file=sys.stderr) print("\n --postroutephysopt", file=sys.stderr) print(" Use post-route physical optimisation in Vivado implementation flow (can improve timing, not recommended by default)", file=sys.stderr) + print("\n --vc707chip", file=sys.stderr) + print(" Sets POLARA_VC707_CHIP rtl define used to recreate Polara chip on VC707 FPGA (False by default)", file=sys.stderr) + print(" Assumes vc707 board is chosen", file=sys.stderr) + print("\n --vc707chipset", file=sys.stderr) + print(" Sets POLARA_VC707_CHIPSET rtl define used to recreate Polara chipset on VC707 FPGA (False by default)", file=sys.stderr) + print(" Assumes vc707 board is chosen", file=sys.stderr) + print("\n --gen2chipset", file=sys.stderr) + print(" Sets POLARA_GEN2_CHIPSET define. Necessary with --se to create the Polara chipset.", file=sys.stderr) + print(" Assumes genesys2 board is chosen", file=sys.stderr) + print("\n --se", file=sys.stderr) + print(" Sets POLARA_GEN2_CHIPSETSE define.", file=sys.stderr) + print(" Assumes genesys2 board is chosen", file=sys.stderr) + print("\n --nocpowertest", file=sys.stderr) + print(" Sets PITON_NOC_POWER_CHIPSET_TEST define.", file=sys.stderr) + print("\n --poloopback", file=sys.stderr) + print(" Sets POLARA_LOOPBACK define.", file=sys.stderr) + print(" To generate packets to test Polara's NOC.", file=sys.stderr) print("\n -h, --help", file=sys.stderr) print(" Display this help message and exit", file=sys.stderr) print("\n", file=sys.stderr) @@ -331,11 +350,23 @@ def runImplFlow(board, design_data, work_dir, log_dir, def_list, slurm, dep_list #os.chdir(dname) print_info("Running FPGA implementation down to bitstream generation") design_board_dir = os.path.join(design_data["PATH"], board) + # Debugging (RR 2024/05) + print("design_board_dir is: ", design_board_dir) impl_log = os.path.join(log_dir, PROJECT_IMPL_LOG) + print("impl_log is: ", impl_log) impl_flow = os.path.join(DV_ROOT, "tools/src/proto/" + tool + "/impl_flow.tcl") + print("impl_flow is: ", impl_flow) jname = "protosyn_impl_%s_%s" % (board, design_data["ID"]) + print("jname is: ", jname) jid = None if (tool == "vivado"): + print("run_vivado called with: ") + print("impl_log, impl_flow") + print("design_data[PATH] is: ", design_data["PATH"]) + print("board is: ", board) + print("slurm is: ", slurm) + print("jname") + print("dep_list is: ", dep_list) jid = run_vivado(impl_log, impl_flow, design_data["PATH"], board, \ slurm, 8, 64000, "6:00:00", jname, dep_list) elif (tool == "ise"): @@ -480,6 +511,12 @@ def setParserOptions(parser): parser.add_option("--axi4_mem", dest="axi4_mem", action="store_true", default=False) parser.add_option("--zeroer_off", dest="zeroer_off", action="store_true", default=False) parser.add_option("--postroutephysopt", dest="postroutephysopt", action="store_true", default=False) + parser.add_option("--vc707chip", dest="polara_vc707_chip_flag", action="store_true", default=False) + parser.add_option("--vc707chipset", dest="polara_vc707_chipset_flag", action="store_true", default=False) + parser.add_option("--gen2chipset", dest="gen2_chipset", action="store_true", default=False) + parser.add_option("--se", dest="se", action="store_true", default=False) + parser.add_option("--nocpowertest", dest="noctest", action="store_true", default=False) + parser.add_option("--poloopback", dest="poloopback", action="store_true", default=False) return parser @@ -490,12 +527,15 @@ def makeDefList(options): #defines.append(df) # disable CSM in this case - if options.core == 'ariane': + if (options.core == 'ariane') or (options.core == 'ara'): defines.append("NO_RTL_CSM") if (options.board == "f1"): print_info("design option is ignored for f1") + if (options.board == "alveou280"): + defines.append("PITON_ALVEO") + # --no-ddr option if (options.no_ddr == True) or (options.board == "piton_board"): defines.append("PITONSYS_NO_MC") @@ -514,7 +554,9 @@ def makeDefList(options): defines.append("PITONSYS_MEM_ZEROER") # do not use SD controller if BRAM is used for boot or a test or if board doesn't have sd - if (options.test_name != None) or (options.board in {"piton_board", 'xupp3r', "f1"}): + # do not use SD controller if using UART boot with genesys2 board + # do not use SD controller if targetting chip to vc707 board + if (options.test_name != None) or (options.board in {"piton_board", "xupp3r", "f1", "alveou280"}) or ((options.board == "genesys2") and (options.uart_dmw == "ddr")) or ((options.design == "chip") and (options.board == "vc707")): pass else: # default option defines.append("PITON_FPGA_SD_BOOT") @@ -541,6 +583,9 @@ def makeDefList(options): # --chip-bridge option if (options.board == "piton_board") and (options.design == "chipset"): pass + # VC707 chip emulation needs the chip bridge + elif (options.design == "chip") and (options.board == "vc707"): + pass # chip-bridge is used for chipset by default elif options.chip_bridge == False and options.design != "chipset": defines.append("PITON_NO_CHIP_BRIDGE") @@ -572,6 +617,9 @@ def makeDefList(options): if options.design == "chipset": if options.board == "piton_board": defines.append("PITON_BOARD_CHIPSET") + # TEST for genesys2 chipset only synthesis + elif options.board == "genesys2": + defines.append("PITON_BOARD_CHIPSET") else: defines.append("PITON_ASIC_CHIPSET") @@ -583,7 +631,9 @@ def makeDefList(options): if options.eth or options.design == "chipset" or options.design == "system": # Ethernet controller is supported on Genesys2 and nexysVideo if options.board == "genesys2" or options.board == "nexysVideo": - defines.append("PITON_FPGA_ETHERNETLITE") + # Don't want ethernet for the Polara chipset + if options.gen2_chipset == False: + defines.append("PITON_FPGA_ETHERNETLITE") else: print_info("--eth option is ignored for %s" % options.board) @@ -604,8 +654,48 @@ def makeDefList(options): print_warning("--oled option is ignored for %s" % options.board) elif options.design == "chipset" and (options.board == "genesys2" or options.board == "nexysVideo"): disp_string = "Heeey! I am a chipset for (Open)Piton Enjoy debugging!" + #disp_string = "Hello" defines.append("{OLED_STRING=\\\"%s\\\"}" % disp_string) + # --vc707chip option + if options.polara_vc707_chip_flag == True: + # Set RTL define + defines.append("POLARA_VC707_CHIP") + + # --vc707chipset option + if options.polara_vc707_chipset_flag == True: + # Set RTL define + defines.append("POLARA_VC707_CHIPSET") + # Set environnment variable + os.environ["POLARA_VC707_CHIPSET"] = "1" + + # --gen2chipset option + if options.gen2_chipset == True: + # Set RTL define + defines.append("POLARA_GEN2_CHIPSET") + # Set environnment variable + os.environ["POLARA_GEN2_CHIPSET"] = "1" + if options.se == True: + # Set RTL define + defines.append("POLARA_GEN2_CHIPSETSE") + # Set environnment variable + os.environ["POLARA_GEN2_CHIPSETSE"] = "1" + + # --nocpowertest option + if options.noctest == True: + # Set RTL define + defines.append("PITON_NOC_POWER_CHIPSET_TEST") + # Set environnment variable + os.environ["PITON_NOC_POWER_CHIPSET_TEST"] = "1" + + # --poloopback option + if options.poloopback == True: + print("poloopback option chosen") + # Set RTL define + defines.append("POLARA_LOOPBACK") + # Set environnment variable + os.environ["POLARA_LOOPBACK"] = "1" + return defines def makeMemMapping(st_brd, work_dir, log_dir): @@ -772,6 +862,15 @@ def main(): os.environ['RTL_SPARC' + str(i)] = "1" print_info('setenv RTL_SPARC' + str(i)) + elif options.core == 'ara': + os.environ['PITON_ARA'] = "1" + os.environ['PITON_RV64_PLATFORM'] = "1" + os.environ['WT_DCACHE'] = "1" + + for i in range(int(options.num_tiles)): + os.environ['RTL_ARA' + str(i)] = "1" + print_info('setenv RTL_ARA' + str(i)) + else: print_error("invalid core configuration " + str(options.core)) sys.exit(1) @@ -845,6 +944,9 @@ def main(): if options.core == 'ariane': config += ' -ariane' + + if options.core == 'ara': + config += ' -ara' print_info("Synthesizing a test: %s" % options.test_name) print_info("Compilation started") diff --git a/piton/tools/src/proto/vivado/setup.tcl b/piton/tools/src/proto/vivado/setup.tcl index b63e811ae..c5a724e40 100644 --- a/piton/tools/src/proto/vivado/setup.tcl +++ b/piton/tools/src/proto/vivado/setup.tcl @@ -34,4 +34,5 @@ set ALL_FILES [concat \ $ALL_COE_FILES \ $ALL_PRJ_IP_FILES \ $ALL_XCI_IP_FILES \ + $ALL_BD_FILES \ ] diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index d5ac3e635..806740c11 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -24,6 +24,7 @@ -model=manycore -toplevel=cmp_top + -config_rtl=SYNTHESIZABLE_BRAM // Uncomment when using simple SRAM models