We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
1 parent ed89c71 commit e1eebe8Copy full SHA for e1eebe8
core/csr_regfile.sv
@@ -1709,7 +1709,7 @@ module csr_regfile
1709
automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPADDR0;
1710
// check if the entry or the entry above is locked
1711
if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index+1].addr_mode == riscv::TOR)) begin
1712
- pmpaddr_d[index] = csr_wdata[CVA6Cfg.PLEN-3:0];
+ pmpaddr_d[index] = {csr_wdata[CVA6Cfg.PLEN-3:1], 1'b0};
1713
end
1714
1715
default: update_access_exception = 1'b1;
0 commit comments