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fix #2657
set bit0 of PMPADDR as read only zero
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core/csr_regfile.sv

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Original file line numberDiff line numberDiff line change
@@ -1709,7 +1709,7 @@ module csr_regfile
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automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPADDR0;
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// check if the entry or the entry above is locked
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if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index+1].addr_mode == riscv::TOR)) begin
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pmpaddr_d[index] = csr_wdata[CVA6Cfg.PLEN-3:0];
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pmpaddr_d[index] = {csr_wdata[CVA6Cfg.PLEN-3:1], 1'b0};
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end
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end
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default: update_access_exception = 1'b1;

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