cebreak tests are failing in latest cva6 riscv-arch-test suite

[spidugu444]

Hi All,

I have an issue with cebreak tests while running in cva6 core for riscv-arch-test suite, it has some gpr mismatch between spike and verilator as shown below.
cebreak.S

Please find the log and csv files as attached.

1. 32-bit cebreak:
   
   

2. 64-bit cebreak:
   
   

cebreak-64-bit log files

spike_cebreak-01_64_bit.csv
spike_cebreak-01_64_bit.log
veri_cebreak-01_64_bit.csv
veri_cebreak-01_64_bit.log

cebreak-32-bit log files

32-bit_veri_cebreak-01.csv
32-bit_veri_cebreak-01.log
32-bit_spike_cebreak-01.csv
32-bit_spike_cebreak-01.log

[MikeOpenHWGroup]

Hi @spidugu444, there has not been any comment on this issue since you created it more than one year ago. Is this issue still unresolved?

[spidugu444]

In this it has an issue with MTVEC default value, on CVA6 RTL it is reading default value as 0x10040 on spike end it is reading 0x0.
please find similar issue here #1312.

[zchamski]

Can be closed as duplicate of #1312.