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It would be really nice to be able to use OpenVizsla to generate USB bus traffic. I would especially like the gateware/software to implement USB host functionality. The host functionality would allow to test whether the device properly handles error conditions like missing ACK or CRC errors, as the errors would be simply scheduled to happen.
I don't know if there is any OpenSource project that already implements such functionality.
Gateware requirements
The gateware would have to support:
Speed selection (LS/FS/HS)
Automated SOF generator (controlled from software, but has to be handled by gateware due to timing requirements)
Transaction handling (e.g. "IN addr 0 ep 0" would make the gateware to send IN packet, wait for DATA packet and acknowledge it, returning the DATA to software)
To simplify the design and improve performance, I think the actual capture could be optional (i.e. if user has multiple units, one would act as generator the other as capture).
The mixed speed (LS transaction followed by FS PRE and SPLIT transactions) are not really essential at the initial stage, but the gateware design should accommodate it.
Software considerations
The software would have to support enumeration (read DEVICE, CONFIGURATION and STRING descriptors and SET ADDRESS). Actual USB handling is probably best left to existing USB stacks. The existing USB stacks can be integrated by implementing USBIP server (OpenVizsla generator software would be USBIP server) - that way only the URB handling would have to be implemented to have a fully working stack. When USBIP server is active it would be nice to have some fault injection mechanism, e.g. corrupt CRC of every 5th OUT bulk packet.
When USBIP is not used, the software should allow manually triggering actions, to allow predefined and/or user-defined compliance-like testcases.
The text was updated successfully, but these errors were encountered:
I think this is more in the scope of https://github.com/greatscottgadgets/luna than OpenVizsla. OpenVizsla was - AFAICT - always about passive tracing and not anything else.
It would be really nice to be able to use OpenVizsla to generate USB bus traffic. I would especially like the gateware/software to implement USB host functionality. The host functionality would allow to test whether the device properly handles error conditions like missing ACK or CRC errors, as the errors would be simply scheduled to happen.
I don't know if there is any OpenSource project that already implements such functionality.
Gateware requirements
The gateware would have to support:
To simplify the design and improve performance, I think the actual capture could be optional (i.e. if user has multiple units, one would act as generator the other as capture).
The mixed speed (LS transaction followed by FS PRE and SPLIT transactions) are not really essential at the initial stage, but the gateware design should accommodate it.
Software considerations
The software would have to support enumeration (read DEVICE, CONFIGURATION and STRING descriptors and SET ADDRESS). Actual USB handling is probably best left to existing USB stacks. The existing USB stacks can be integrated by implementing USBIP server (OpenVizsla generator software would be USBIP server) - that way only the URB handling would have to be implemented to have a fully working stack. When USBIP server is active it would be nice to have some fault injection mechanism, e.g. corrupt CRC of every 5th OUT bulk packet.
When USBIP is not used, the software should allow manually triggering actions, to allow predefined and/or user-defined compliance-like testcases.
The text was updated successfully, but these errors were encountered: