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AArch64: Assertion fails isImmediateEncodable(ImmediateOp.ORR, imm64)
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compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/lir/aarch64/AArch64PermuteOp.java

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2021, 2025, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
@@ -139,9 +139,10 @@ public void emitCode(CompilationResultBuilder crb, AArch64MacroAssembler masm) {
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// indices v * 2, v * 2 + 1 until we reach the element width equal to Byte.SIZE
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if (eKind.getSizeInBytes() == AArch64Kind.QWORD.getSizeInBytes()) {
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masm.neon.shlVVI(vSize, ElementSize.DoubleWord, xtmp1Reg, currentIdxReg, 1);
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masm.neon.shlVVI(vSize, ElementSize.DoubleWord, xtmp2Reg, xtmp1Reg, Integer.SIZE);
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masm.neon.moveVV(vSize, xtmp2Reg, xtmp1Reg);
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masm.neon.orrVI(vSize, ElementSize.Word, xtmp2Reg, 1);
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masm.neon.shlVVI(vSize, ElementSize.DoubleWord, xtmp2Reg, xtmp2Reg, Integer.SIZE);
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masm.neon.orrVVV(vSize, xtmp1Reg, xtmp1Reg, xtmp2Reg);
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masm.neon.orrVI(vSize, ElementSize.DoubleWord, xtmp1Reg, 1L << Integer.SIZE);
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currentIdxReg = xtmp1Reg;
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eKind = AArch64Kind.DWORD;
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}

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