Repositories list

• SOC

  Public
  Verilog

  •0•0•0•0•Updated Mar 4, 2025Mar 4, 2025

• AXI4-Frame-Fetch

  Public
  Verilog

  •0•0•0•0•Updated Feb 26, 2025Feb 26, 2025

• HOG_SVM_FPGA

  Public
  SystemVerilog

  •0•0•0•0•Updated Feb 21, 2025Feb 21, 2025

• DBI-TX-Controller

  Public
  This repository contains the RTL code of a MIPI DBI (TX) Controller with AXI4 interface in the application layer.

  Verilog

  •0•0•0•0•Updated Feb 5, 2025Feb 5, 2025

• SCCB-Master-Controller

  Public
  Verilog

  •0•0•0•0•Updated Jan 17, 2025Jan 17, 2025

• .github

  Public
  0•0•0•0•Updated Jan 3, 2025Jan 3, 2025

• AXI4-Interconnect

  Public
  SystemVerilog

  •0•0•0•0•Updated Nov 3, 2024Nov 3, 2024