aarch64: add recursive linear mapper to boot process

Cargo.toml

@@ -70,6 +70,7 @@ missing_errors_doc = "allow"
 struct_field_names = "allow"
 items_after_statements = "allow"
 cast_possible_truncation = "allow" # TODO(qix-): Temporary until the virt/phys types land.
+assertions_on_constants = "allow"
 
 [profile.dev]
 panic = "abort"            # Use "abort" panic strategy

oro-arch-aarch64/src/asm.rs

@@ -7,19 +7,31 @@ use core::arch::asm;
 ///
 /// # Safety
 /// Caller must ensure that the virtual address is valid and aligned.
-pub unsafe fn invalidate_tlb_el1(virt: usize) {
+pub unsafe fn invalidate_tlb_el1<T>(virt: *const T) {
 	asm!(
 		"dsb ish",                // Ensure the update is visible
 		"dc ivac, {0:x}",         // Invalidate the data cache by virtual address
 		"ic ivau, {0:x}",         // Invalidate the instruction cache by virtual address
 		"tlbi vaae1, {0}",        // Invalidate the TLB entry by virtual address for EL1
 		"dsb ish",                // Ensure completion of the invalidation
 		"isb",                    // Synchronize the instruction stream
-		in(reg) virt,
+		in(reg) virt as u64,
 		options(nostack, preserves_flags),
 	);
 }
 
+/// Invalidates the entire TLB.
+pub fn invalid_tlb_el1_all() {
+	unsafe {
+		asm!(
+			"tlbi vmalle1",
+			"dsb ish",
+			"isb",
+			options(nostack, preserves_flags),
+		);
+	}
+}
+
 /// Loads the current `TTBR0_EL1` register value.
 ///
 /// # Safety