espi_regs.rdl

// Copyright 2024 Oxide Computer Company
// This is SystemRDL description of the sw-accessible registers in the Gimlet
// Sequencer FPGA.

property addr_span_bytes {
    type=number;
    component=addrmap;
    default=0x100;
    };

addrmap espi_regs {
    
    name = "espi system registers";
    desc = "Registers accessible on the Axi bus for debug and testing of the espi target";

    default regwidth = 32;
    default sw = rw;
    default hw = r;

    reg {
        name = "Flags Register";
        desc = "";

        field {
            default sw = woclr;
            desc = "Sticky bit for alert, set to 1 when alert is needed, cleared by writing 1";
        } alert[0:0] =  0;
    } flags;

    reg {
        name = "Control Register";
        desc = "";
        field {
            desc = "Respond back on periph 0 channel vs oob";
        } msg_en[4:4] =  0;
        field {
            desc = "Set to one to reset the command FIFO. Cleared by hardware after reset.";
        } cmd_fifo_reset[3:3] =  0;
         field {
            desc = "Set to one to reset the command size FIFO. Cleared by hardware after reset.";
        } cmd_size_fifo_reset[2:2] =  0;
        field {
            desc = "Set to one to reset response FIFO. Cleared by hardware after reset.";
        } resp_fifo_reset[1:1] =  0;
        field {
            desc = "Set to one mux in the debug FIFOs and ignore the real eSPI interface";
        } dbg_mode_en[0:0] =  0;   
    } control;

    reg {
        name = "Status Register";
        desc = "";

        field {
            default sw = r;
            desc = "Set to one to 1 when hw is running the spi transaction, no new transactions
            may be issued until it is finished. Technically represents cs_n being low.";
        } busy[0:0] =  0;

    } status;

    reg {
        name = "Fifo Status Register";
        desc = "";
        field {
            default sw = r;
            desc = "Show used words in command FIFO (word = 32bits/4 bytes),
            1024 words so 4kB";
        } cmd_used_wds[31:16] =  0;

        field {
            default sw = r;
            desc = "Show used FIFO words in response FIFO (word = 32bits/4 bytes),
            1024 words so 4kB";
        } resp_used_wds[15:0] =  0;
    } fifo_status;

    reg {
        name = "Command FIFO Write Data Register";
        desc = "";
        field {
            desc = "Writing stores data in fifo";
        } fifo_data[31:0] =  0;
     } cmd_fifo_wdata;

    reg {
        name = "Response FIFO Read Data Register";
        desc = "";
        field {
            desc = "Note: Reading side-effects the data by popping the fifo";
        } fifo_data[31:0] =  0;
    } resp_fifo_rdata;

    reg {
        name = "Command FIFO Byte Count FIFO";
        desc = "";
        field {
            desc = "store command byte size in fifo. Beacause we are sending 4bytes at a time into the fifo, but only reading
            1 byte at a time, we need to store the number of cmd bytes in the fifo. This allows queueing up multiple commands
            if desired. left over data bytes are discarded if this fifo is empty and there are <4 bytes left in cmd_fifo";
        } fifo_data[7:0] =  0;
     } cmd_size_fifo_wdata;

    reg {
        name = "UART Avail Threshold Bytes";
        desc = "";
        field {
            desc = "";
        } bytes[7:0] =  32;
     } uart_thresh;
};