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Commit 18aee91

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nathanaelhuffmannathanaelhuffman
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RDL naming convention enforcement and updates
1 parent cf0a4bd commit 18aee91

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19 files changed

+313
-48
lines changed

19 files changed

+313
-48
lines changed

‎hdl/ip/vhd/espi/BUCK

+6-6
Original file line numberDiff line numberDiff line change
@@ -2,21 +2,21 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
22
load("//tools:rdl.bzl", "rdl_file")
33

44
rdl_file(
5-
name = "espi_spec_regs_pkg",
5+
name = "espi_spec_regs_rdl",
66
src = "espi_spec_regs.rdl",
77
outputs = ["espi_spec_regs_pkg.vhd", "espi_spec_regs.html"],
88
visibility = ['PUBLIC']
99
)
1010

1111
rdl_file(
12-
name = "vwire_regs_pkg",
12+
name = "vwire_regs_rdl",
1313
src = "vwire_channel/vwire_regs.rdl",
1414
outputs = ["vwire_regs_pkg.vhd", "vwire_regs.html"],
1515
visibility = ['PUBLIC']
1616
)
1717

1818
rdl_file(
19-
name = "espi_regs_pkg",
19+
name = "espi_regs_rdl",
2020
src = "sys_regs/espi_regs.rdl",
2121
outputs = ["espi_regs_pkg.vhd", "espi_regs.html"],
2222
visibility = ['PUBLIC']
@@ -33,9 +33,9 @@ vhdl_unit(
3333
"vwire_channel/*.vhd",
3434
"*.vhd"]),
3535
deps = [
36-
":espi_spec_regs_pkg",
37-
":espi_regs_pkg",
38-
":vwire_regs_pkg",
36+
":espi_spec_regs_rdl",
37+
":espi_regs_rdl",
38+
":vwire_regs_rdl",
3939
"//hdl/ip/vhd/common:calc_pkg",
4040
"//hdl/ip/vhd/common:time_pkg",
4141
"//hdl/ip/vhd/synchronizers:meta_sync",

‎hdl/ip/vhd/espi/sys_regs/espi_regs.rdl

+7
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,14 @@
22
// This is SystemRDL description of the sw-accessible registers in the Gimlet
33
// Sequencer FPGA.
44

5+
property addr_span_bytes {
6+
type=number;
7+
component=addrmap;
8+
default=0x100;
9+
};
10+
511
addrmap espi_regs {
12+
613
name = "espi system registers";
714
desc = "Registers accessible on the Axi bus for debug and testing of the espi target";
815

‎hdl/ip/vhd/i2c/controller/BUCK

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
22
load("//tools:rdl.bzl", "rdl_file")
33

44
rdl_file(
5-
name = "i2c_ctrl_regs_pkg",
5+
name = "i2c_ctrl_regs_rdl",
66
src = "regs/i2c_ctrl_regs.rdl",
77
outputs = ["i2c_ctrl_regs_pkg.vhd", "i2c_ctrl_regs.html"],
88
visibility = ['PUBLIC']

‎hdl/ip/vhd/i2c/io_expanders/PCA9506ish/BUCK

+3-3
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
22
load("//tools:rdl.bzl", "rdl_file")
33

44
rdl_file(
5-
name = "pca9506_regs_pkg",
5+
name = "pca9506_regs_rdl",
66
src = "pca9506_regs.rdl",
7-
outputs = ["pca9506_regs_pkg.vhd", "pca9506_regs_pkg.html"],
7+
outputs = ["pca9506_regs_pkg.vhd", "pca9506_regs.html"],
88
visibility = ['PUBLIC']
99
)
1010

@@ -13,7 +13,7 @@ vhdl_unit(
1313
srcs = glob(["*.vhd"]),
1414
deps = [
1515
"//hdl/ip/vhd/i2c/target:i2c_target_phy",
16-
":pca9506_regs_pkg",
16+
":pca9506_regs_rdl",
1717
],
1818
visibility = ['PUBLIC']
1919
)

‎hdl/ip/vhd/i2c/muxes/PCA9545ish/BUCK

+3-3
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
22
load("//tools:rdl.bzl", "rdl_file")
33

44
rdl_file(
5-
name = "i2c_mux_regs_pkg",
5+
name = "emulated_pca9545_regs_rdl",
66
src = "emulated_pca9545_regs.rdl",
7-
outputs = ["i2c_mux_regs_pkg.vhd", "i2c_mux_regs.html"],
7+
outputs = ["emulated_pca9545_regs_pkg.vhd", "emulated_pca9545_regs.html"],
88
visibility = ['PUBLIC']
99
)
1010

@@ -14,7 +14,7 @@ vhdl_unit(
1414
srcs = glob(["*.vhd"]),
1515
deps = [
1616
"//hdl/ip/vhd/i2c/target:i2c_target_phy",
17-
":i2c_mux_regs_pkg",
17+
":emulated_pca9545_regs_rdl",
1818
],
1919
visibility = ['PUBLIC']
2020
)

‎hdl/ip/vhd/i2c/muxes/PCA9545ish/emulated_pca9545_regs.rdl

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// Copyright 2025 Oxide Computer Company
22
// This is SystemRDL description of emulated i2c mux registers
33

4-
addrmap emulated_pca9545 {
4+
addrmap emulated_pca9545_regs {
55
name = "pca9545 registers";
66
desc = "Registers accessible on the i2c bus for controlling the emulated PCA9545 i2c mux";
77

‎hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_function.vhd

+1-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ use ieee.numeric_std.all;
1616
use ieee.numeric_std_unsigned.all;
1717

1818
use work.i2c_base_types_pkg.all;
19-
use work.i2c_mux_regs_pkg.all;
19+
use work.emulated_pca9545_regs_pkg.all;
2020

2121

2222
entity pca9545ish_function is

‎hdl/ip/vhd/info/BUCK

+2-2
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
22
load("//tools:rdl.bzl", "rdl_file")
33

44
rdl_file(
5-
name = "info_regs_pkg",
5+
name = "info_regs_rdl",
66
src = "info_regs.rdl",
77
outputs = ["info_regs_pkg.vhd", "info_regs.html"],
88
visibility = ['PUBLIC']
@@ -32,7 +32,7 @@ vhdl_unit(
3232
srcs = ["info_2k8.vhd"],
3333
deps = [
3434
":git_sha_pkg",
35-
":info_regs_pkg",
35+
":info_regs_rdl",
3636
],
3737
standard = "2008",
3838
visibility = ['PUBLIC']

‎hdl/ip/vhd/spi_nor_controller/BUCK

+4-4
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,12 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
22
load("//tools:rdl.bzl", "rdl_file")
33

44
rdl_file(
5-
name = "spi_nor_rdl",
5+
name = "spi_nor_regs_rdl",
66
src = "spi_nor_regs.rdl",
77
outputs = [
88
"spi_nor_regs_pkg.vhd",
9-
"spi_nor_reg_map.html",
10-
"spi_nor_reg_map.json",
9+
"spi_nor_regs.html",
10+
"spi_nor_regs.json",
1111
],
1212
visibility = ["PUBLIC"],
1313
)
@@ -23,7 +23,7 @@ vhdl_unit(
2323
]),
2424
standard = "2019",
2525
deps = [
26-
":spi_nor_rdl",
26+
":spi_nor_regs_rdl",
2727
"//hdl/ip/vhd/fifos:dcfifo_xpm",
2828
"//hdl/ip/vhd/axi_blocks:axilite_if_2k19_pkg",
2929
],

‎hdl/ip/vhd/spi_nor_controller/spi_nor_regs.rdl

+1-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
// This is SystemRDL description of the sw-accesible registers in the
88
// grapefruit dev board FPGA.
99

10-
addrmap nor_flash_regs {
10+
addrmap spi_nor_regs {
1111
name = "SPI/QSPI NOR flash controller";
1212
desc = "";
1313

‎hdl/projects/grapefruit/BUCK

+19-19
Original file line numberDiff line numberDiff line change
@@ -3,37 +3,37 @@ load("//tools:rdl.bzl", "rdl_file")
33
load("//tools:vivado.bzl", "vivado_bitstream")
44

55
rdl_file(
6-
name = "base_regs_map",
6+
name = "gfruit_regs_rdl",
77
src = "base_regs/gfruit_regs.rdl",
88
outputs = [
9-
"grapefruit_regs_pkg.vhd",
10-
"grapefruit_reg_map.html",
11-
"grapefruit_reg_map.json",
9+
"gfruit_regs_pkg.vhd",
10+
"gfruit_regs.html",
11+
"gfruit_regs.json",
1212
]
1313
)
1414

1515
rdl_file(
16-
name = "gfruit_sgpio_regs",
17-
src = "sgpio/gfruit_sgpio.rdl",
16+
name = "gfruit_sgpio_regs_rdl",
17+
src = "sgpio/gfruit_sgpio_regs.rdl",
1818
outputs = [
19-
"sgpio_regs_pkg.vhd",
20-
"sgpio_reg_map.html",
21-
"sgpio_reg_map.json",
19+
"gfruit_sgpio_regs_pkg.vhd",
20+
"gfruit_sgpio_regs.html",
21+
"gfruit_sgpio_regs.json",
2222
]
2323
)
2424

2525
rdl_file(
26-
name = "gfruit_top_regs",
26+
name = "gfruit_top_rdl",
2727
src = "gfruit_top.rdl",
2828
deps = [
29-
":base_regs_map",
30-
":gfruit_sgpio_regs",
31-
"//hdl/ip/vhd/spi_nor_controller:spi_nor_rdl",
32-
"//hdl/ip/vhd/espi:espi_regs_pkg",
29+
":gfruit_regs_rdl",
30+
":gfruit_sgpio_regs_rdl",
31+
"//hdl/ip/vhd/spi_nor_controller:spi_nor_regs_rdl",
32+
"//hdl/ip/vhd/espi:espi_regs_rdl",
3333
],
3434
outputs = [
35-
"gfruit_top_map.html",
36-
"gfruit_top_map.json"
35+
"gfruit_top.html",
36+
"gfruit_top.json"
3737
]
3838
)
3939

@@ -46,7 +46,7 @@ vhdl_unit (
4646
name = "base_regs",
4747
srcs = glob(["base_regs/*.vhd"]),
4848
deps = [
49-
":base_regs_map",
49+
":gfruit_regs_rdl",
5050
"//hdl/ip/vhd/axi_blocks:axilite_if_2k19_pkg",
5151
],
5252
standard = "2019",
@@ -56,7 +56,7 @@ vhdl_unit (
5656
name = "gfruit_sgpio",
5757
srcs = glob(["sgpio/*.vhd"]),
5858
deps = [
59-
":gfruit_sgpio_regs",
59+
":gfruit_sgpio_regs_rdl",
6060
"//hdl/ip/vhd/axi_blocks:axilite_if_2k19_pkg",
6161
"//hdl/ip/vhd/sgpio:sgpio_top",
6262
],
@@ -69,7 +69,7 @@ vhdl_unit(
6969
srcs = ["grapefruit_top.vhd"],
7070
deps = [
7171
":base_regs",
72-
":gfruit_top_regs",
72+
":gfruit_top_rdl",
7373
":gfruit_sgpio",
7474
":gfruit_black_boxes",
7575
"//hdl/projects/cosmo_seq:reset_sync",

‎hdl/projects/grapefruit/base_regs/gfruit_regs.rdl

+1-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
// This is SystemRDL description of the sw-accesible registers in the
88
// grapefruit dev board FPGA.
99

10-
addrmap gfruit_base_regs {
10+
addrmap gfruit_regs {
1111
name = "Grapefruit FPGA";
1212
desc = "Register description of the Grapefruit FPGA";
1313

‎hdl/projects/grapefruit/base_regs/registers.vhd

+1-1
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ use ieee.numeric_std_unsigned.all;
1313
use work.axil_common_pkg.all;
1414
use work.axil8x32_pkg;
1515

16-
use work.grapefruit_regs_pkg.all;
16+
use work.gfruit_regs_pkg.all;
1717

1818
entity registers is
1919
port (

‎hdl/projects/grapefruit/gfruit_top.rdl

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
addrmap top_level_map {
22
default regwidth = 32;
33
// Instantiate 2 to test nesting
4-
gfruit_base_regs base @ 0x0;
5-
nor_flash_regs spi_nor @ 0x0100;
4+
gfruit_regs base @ 0x0;
5+
spi_nor_regs spi_nor @ 0x0100;
66
espi_regs espi @ 0x0200;
7-
gfruit_sgpio sgpio @ 0x0300;
7+
gfruit_sgpio_regs sgpio @ 0x0300;
88
};

‎hdl/projects/grapefruit/sgpio/gfruit_sgpio.vhd

+1-1
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ use ieee.numeric_std_unsigned.all;
1818

1919
use work.axil8x32_pkg.all;
2020

21-
use work.sgpio_regs_pkg.all;
21+
use work.gfruit_sgpio_regs_pkg.all;
2222

2323
entity gfruit_sgpio is
2424
port (

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