I2C Controller: add proper glitch filtering on SDA

Author: Aaron-Hartwig

hdl/ip/vhd/i2c/common/BUCK

@@ -16,7 +16,8 @@ vhdl_unit(
     name = "i2c_glitch_filter",
     srcs = ["i2c_glitch_filter.vhd"],
     deps = [
-       "//hdl/ip/vhd/synchronizers:meta_sync",
+        "//hdl/ip/vhd/common:transforms_pkg",
+        "//hdl/ip/vhd/synchronizers:meta_sync",
     ],
     visibility = ['PUBLIC']
 )

hdl/ip/vhd/i2c/common/i2c_common_pkg.vhd

@@ -27,6 +27,7 @@ package i2c_common_pkg is
         sta_su_hd_ns    : positive; -- START set-up/hold time
         sto_su_ns       : positive; -- STOP set-up time
         sto_sta_buf_ns  : positive; -- bus free time between STOP and START
+        tsp_ns          : positive; -- pulse width of spikes to be suppressed by the input filter
     end record;
 
     function get_i2c_settings (constant mode : mode_t) return settings_t;
@@ -65,23 +66,26 @@ package body i2c_common_pkg is
                     250,
                     4700,
                     4000,
-                    4700
+                    4700,
+                    50 -- this is technically undefined in the spec
                  );
             when FAST =>
                 r := (
                     2500, -- 10^9 / 400_000Hz
                     100,
                     600,
                     600,
-                    1300
+                    1300,
+                    50
                 );
             when FAST_PLUS =>
                 r := (
                     1000, -- 10^9 / 1_000_000Hz
                     50,
                     260,
                     260,
-                    500
+                    500,
+                    50
                 );
         end case;
 

hdl/ip/vhd/i2c/common/i2c_glitch_filter.vhd

@@ -18,6 +18,8 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.numeric_std_unsigned.all;
 
+use work.transforms_pkg.shift_in_at_0;
+
 entity i2c_glitch_filter is
     generic(
         -- number of register stages the n filter pipeline
@@ -86,11 +88,9 @@ begin
             last_sda <= filtered_sda;
             -- Using variables here to make the filtered outputs
             -- simultaneous more easily
-            nxt_scl_pipe := shift_left(scl_pipe, 1);
-            nxt_scl_pipe(0) := scl_syncd;
+            nxt_scl_pipe := shift_in_at_0(scl_pipe, scl_syncd);
             scl_pipe <= nxt_scl_pipe;  -- do the register assignment
-            nxt_sda_pipe := shift_left(sda_pipe, 1);
-            nxt_sda_pipe(0) := sda_syncd;
+            nxt_sda_pipe := shift_in_at_0(sda_pipe, sda_syncd);
             sda_pipe <= nxt_sda_pipe;  -- do the register assignment
 
             -- we use the variables set above here to make the filtered outputs

hdl/ip/vhd/i2c/controller/BUCK

@@ -15,6 +15,7 @@ vhdl_unit(
         "txn_layer/*.vhd",]),
     deps = [
         "//hdl/ip/vhd/i2c/common:i2c_common_pkg",
+        "//hdl/ip/vhd/i2c/common:i2c_glitch_filter",
         "//hdl/ip/vhd/common:countdown",
         "//hdl/ip/vhd/common:strobe",
         "//hdl/ip/vhd/common:streaming_if_pkg",

hdl/ip/vhd/i2c/controller/link_layer/i2c_ctrl_link_layer.vhd

@@ -77,6 +77,8 @@ architecture rtl of i2c_ctrl_link_layer is
     constant SDA_TRANSITION_TICKS   : positive :=
         to_integer(calc_ns(300, CLK_PER_NS, 5));
 
+    constant TSP_TICKS : positive := to_integer(calc_ns(SETTINGS.tsp_ns, CLK_PER_NS, 8));
+
     type state_t is (
         IDLE,
         WAIT_TBUF,
@@ -198,15 +200,22 @@ begin
     -- SDA Control
     --
 
-    -- TODO: this should be a glitch filter that means `tsp` per the spec
-    sda_in_sync: entity work.meta_sync
-        generic map (
-            STAGES      => 2
+    -- Right now the controller doesn't need much of what this block offers aside from SDA filtering
+    i2c_glitch_filter_inst: entity work.i2c_glitch_filter
+        generic map(
+            filter_cycles   => TSP_TICKS
         )
         port map(
-          async_input   => sda_if.i,
-          clk           => clk,
-          sycnd_output  => sda_in_syncd
+            clk             => clk,
+            reset           => reset,
+            raw_scl         => '1',
+            raw_sda         => sda_if.i,
+            filtered_scl    => open,
+            scl_fedge       => open,
+            scl_redge       => open,
+            filtered_sda    => sda_in_syncd,
+            sda_fedge       => open,
+            sda_redge       => open
         );
 
     -- This counter enforces `tvd` per the spec, ensuring we transition SDA only after an