SPI<->AXI interface

Author: nathanaelhuffman

hdl/ip/vhd/spi/axi_controller/BUCK

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+load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
+load("//tools:rdl.bzl", "rdl_file")
+
+
+vhdl_unit(
+    name = "spi_axi_controller",
+    srcs = glob(["*.vhd",]),
+        deps = [
+            "//hdl/ip/vhd/spi/spi_target_phy:spi_target_phy",
+    ],
+    visibility = ['PUBLIC']
+)
+
+vunit_sim(
+    name = "spi_axi_tb",
+    srcs = glob(["sims/**/*.vhd"]),
+    deps = [
+        ":spi_axi_controller",
+        "//hdl/ip/vhd/vunit_components:spi_vcs",
+        "//hdl/ip/vhd/i2c/target:i2c_phy_consolidator",
+    ],
+    visibility = ['PUBLIC'],
+)

hdl/ip/vhd/spi/axi_controller/docs/README.adoc

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+It supports Mode 0 (0,0) and mode3 (1,1) transfers. It is expected that there are fewer than 256 addressable registers, but we’re picking 16bit addressing for future extensibility without changing the protocol and to support a circular buffer for storing event history.
+
+SPI instructions
+[cols=4,options="header"]
+|===
+|Opcode| Instruction Name | Description| Notes
+| 0x0 | Write byte(s)      | Write one or more contiguous bytes | 
+| 0x1|  Read byte(s)      | Read one or more contiguous bytes|
+| 0x2| Bit set | hardware does a bit-wise OR with data and current register state | new_reg = old_reg \|\| data
+| 0x3| Bit clr | hardware does a bit-wise clear with data and current register state |new_reg = old_reg && !data
+|===
+
+Note that for the bit-set and bit-clear spi instructions, the AXI controller internally does a read-modify-write operation, resulting
+in a read of the current register state, a bitwise operation with the data, and a write back of the new register state.  These are
+not good operations to use if the registers you're modifiying have read-side effects.

hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb.vhd

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+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.numeric_std_unsigned.all;
+
+library vunit_lib;
+    context vunit_lib.com_context;
+    context vunit_lib.vunit_context;
+    context vunit_lib.vc_context;
+
+use vunit_lib.spi_pkg.all;
+
+use work.spi_axi_tb_pkg.all;
+use work.spi_axi_pkg.all;
+
+
+entity spi_axi_tb is
+    generic (
+
+        runner_cfg : string
+    );
+end entity;
+
+architecture tb of spi_axi_tb is
+
+begin
+
+    th: entity work.spi_axi_th;
+
+    bench: process
+        alias reset is << signal th.reset : std_logic >>;
+        alias csn is << signal th.csn : std_logic >>;
+        variable buf           : buffer_t;
+        variable data          : std_logic_vector(7 downto 0) := (others => '0');
+        variable expected_data : std_logic_vector(7 downto 0) := (others => '0');
+        variable address       : std_logic_vector(15 downto 0) := (others => '0');
+        alias addr_h           : std_logic_vector(7 downto 0) is address(15 downto 8);
+        alias addr_l           : std_logic_vector(7 downto 0) is address(7 downto 0);
+    begin
+        -- Always the first thing in the process, set up things for the VUnit test runner
+        test_runner_setup(runner, runner_cfg);
+        show_all(rd_logger, display_handler);
+        -- Reach into the test harness, which generates and de-asserts reset and hold the
+        -- test cases off until we're out of reset. This runs for every test case
+        wait until reset = '0';
+        wait for 500 ns;  -- let the resets propagate
+
+        while test_suite loop
+            if run("single-read") then
+                -- set up the "memory to be read with a known value"
+                buf := allocate(rmemory, 1 * 64, alignment => 8);
+                -- Use the simulation interface to set the data we're going to read back
+                expected_data := X"AA";
+                write_word(rmemory, 0, expected_data);
+                -- TB will fault if DUT tries to write to this memory
+                set_permissions(rmemory, 0, read_only);
+                -- Read back written word via sim interface and check it matches
+                data := read_word(rmemory, 0, 1);
+                check_equal(data, expected_data, "AXI ram setup didn't work correctly");
+                -- issue spi read command
+                csn <= '0';
+                -- read opcode
+                push_stream(net, master_wstream, resize(spi_opcode_read, 8));
+                -- addr h
+                push_stream(net, master_wstream, addr_h);
+                -- addr l
+                push_stream(net, master_wstream, addr_l);
+                -- data
+                push_stream(net, master_wstream, x"00");
+                wait_until_idle(net, as_sync(master_spi));
+                csn <= '1';
+                -- Read back word rx'd from DUT and check it matches expected.
+                -- -- we're going to have 3 dummy bytes here, skip them, keeping the 4th
+                for i in 0 to 3 loop
+                    pop_stream(net, master_rstream, data);
+                end loop;
+                check_equal(data, expected_data, "Read data did not match expected");
+
+    
+                -- get response back
+                -- check against known value
+
+            -- single write
+            -- single bit-set
+            -- single bit-clear
+            -- multi-read
+            -- multi-write
+            -- Note: by and large, multi-bit-set/clr doesn't really make sense over this interface
+            -- it may still work, do we need to test it?
+            -- invalid transaction, ok after
+            -- early termination of transaction, ok after
+            end if;
+        end loop;
+
+        wait for 2 us;
+        test_runner_cleanup(runner);
+        wait;
+    end process;
+
+    -- Example total test timeout dog
+    test_runner_watchdog(runner, 10 ms);
+
+end tb;

hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb_pkg.vhd

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+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2025 Oxide Computer Company
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library vunit_lib;
+    context vunit_lib.vunit_context;
+    context vunit_lib.com_context;
+    context vunit_lib.vc_context;
+
+use vunit_lib.spi_pkg.all;
+
+package spi_axi_tb_pkg is
+
+    constant rd_logger       : logger_t    := get_logger("axi_rd");
+    constant rmemory         : memory_t    := new_memory;
+    constant axi_read_target : axi_slave_t := new_axi_slave(address_fifo_depth => 1,
+                                                            memory => rmemory,
+                                                            logger => rd_logger);
+
+    constant wmemory          : memory_t    := new_memory;
+    constant axi_write_target : axi_slave_t := new_axi_slave(memory => wmemory);
+
+
+    constant master_spi : spi_master_t := new_spi_master;
+    constant master_wstream : stream_master_t := as_stream(master_spi);
+    constant master_rstream : stream_slave_t := as_stream(master_spi);
+
+end package;

hdl/ip/vhd/spi/axi_controller/sims/spi_axi_th.vhd

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+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library vunit_lib;
+    context vunit_lib.vunit_context;
+    context vunit_lib.com_context;
+    context vunit_lib.vc_context;
+
+use work.spi_axi_tb_pkg.all;
+
+entity spi_axi_th is
+end entity;
+
+architecture th of spi_axi_th is
+
+    signal clk   : std_logic := '0';
+    signal reset : std_logic := '1';
+
+    signal csn : std_logic := '1';
+    signal sclk : std_logic;
+    signal copi : std_logic;
+    signal cipo : std_logic;
+    signal awvalid : std_logic;
+    signal awready : std_logic;
+    signal awaddr : std_logic_vector(15 downto 0);
+    signal wvalid : std_logic;
+    signal wready : std_logic;
+    signal wdata : std_logic_vector(7 downto 0);
+    signal wstrb : std_logic_vector(3 downto 0);
+    signal bvalid : std_logic;
+    signal bready : std_logic;
+    signal bresp : std_logic_vector(1 downto 0);
+    signal arvalid : std_logic;
+    signal arready : std_logic;
+    signal araddr : std_logic_vector(15 downto 0);
+    signal rvalid : std_logic;
+    signal rready : std_logic;
+    signal rdata : std_logic_vector(7 downto 0);
+    signal rresp : std_logic_vector(1 downto 0);
+
+    signal arid             : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(0, 4));
+    signal bid              : std_logic_vector(3 downto 0);
+    signal awid             : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(0, 4));
+    signal rid              : std_logic_vector(3 downto 0);
+
+begin
+
+    -- set up a fastish clock for the sim env
+    -- and release reset after a bit of time
+    clk   <= not clk after 4 ns;
+    reset <= '0' after 200 ns;
+
+
+    DUT: entity work.spi_axi_controller
+     port map(
+        clk => clk,
+        reset => reset,
+        csn => csn,
+        sclk => sclk,
+        copi => copi,
+        cipo => cipo,
+        awvalid => awvalid,
+        awready => awready,
+        awaddr => awaddr,
+        wvalid => wvalid,
+        wready => wready,
+        wdata => wdata,
+        wstrb => wstrb,
+        bvalid => bvalid,
+        bready => bready,
+        bresp => bresp,
+        arvalid => arvalid,
+        arready => arready,
+        araddr => araddr,
+        rvalid => rvalid,
+        rready => rready,
+        rdata => rdata,
+        rresp => rresp
+    );
+
+    -- sim infrastructure from VUnit
+    axi_read_sim_infra: entity vunit_lib.axi_read_slave
+        generic map (
+            axi_slave => axi_read_target
+        )
+        port map (
+            aclk => clk,
+
+            arvalid => arvalid,
+            arready => arready,
+            arid    => arid,
+            araddr  => araddr,
+            arlen   => "00000000",
+            arsize  => "000",
+            arburst => "00",
+
+            rvalid => rvalid,
+            rready => rready,
+            rid    => rid,
+            rdata  => rdata,
+            rresp  => rresp,
+            rlast  => open
+        );
+
+    axi_write_sim_infra: entity vunit_lib.axi_write_slave
+        generic map (
+            axi_slave => axi_write_target
+        )
+        port map (
+            aclk    => clk,
+            awvalid => awvalid,
+            awready => awready,
+            awid    => awid,
+            awaddr  => awaddr,
+            awlen   => "00000000",
+            awsize  => "000",
+            awburst => "00",
+            wvalid  => wvalid,
+            wready  => wready,
+            wdata   => wdata,
+            wstrb   => wstrb,
+            wlast   => '1',
+            bvalid  => bvalid,
+            bready  => bready,
+            bid     => bid,
+            bresp   => open
+        );
+
+    spi_controller: entity vunit_lib.spi_master
+    generic map(
+        spi => master_spi
+    )
+    port map (
+        sclk => sclk,
+        mosi => copi,
+        miso => cipo
+    );
+
+
+end th;