Fix inferred latch and sensitivity list miss (#298)

Author: nathanaelhuffman

hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd

@@ -109,7 +109,7 @@ begin
     --  avail:
     --   if we read down to empty, move to not avail
 
-    orphan_timer: process(clk)
+    orphan_timer: process(clk, reset)
     begin
         if reset then
             fifo_thresh_timer <= (others => '0');

hdl/ip/vhd/espi/txn_layer/link_to_txn_bridge.vhd

@@ -135,6 +135,7 @@ qspi_resp_fifo: entity work.dcfifo_xpm
             -- NORMAL MODE
             txn_cmd.valid <= not qspi_cmd_slow_rempty;
             txn_cmd.data <= qspi_cmd_slow_rdata;
+            gen_cmd.ready <= '0';
             -- we don't drive qspi_cmd here b/c it's a fast signal
             qspi_cmd_rdack <= txn_cmd.valid and txn_cmd.ready;
             gen_resp.valid <= '0';